US3609688A
Expired / Lapsed
US
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Code translator for use in an associative memory system
Assignee: AT&T Inc
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Filing: 1969-09-03
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Granted: 1971-09-28
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Expires: 1989-09-03
Abstract
Abstract A diode code translator circuit is described in which inhibiting transistors are driven by coded output signals to inhibit concurrent input signals in a predetermined priority pattern. The uninhibited input signals drive an OR gate to provide a transfer signal for gating the coded output signals. A system for cascading the code translator circuits of this invention is also shown in which the transfer signals from a plurality of the code translator circuits serve as input signals to a succeeding stage. The transfer signal from the succeeding stage serves as the gating signal. In this arrangement, the coded output signals from the plurality of code translation circuits are connected in parallel to extend the priority sequence to the cascaded system.
Inventors
- 👤 James T Koo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:08
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
79 words
A code translator circuit having a set of output lines and a plurality of input signal buses in which a different predetermined coded signal is provided on said set of output lines in response to a signal applied to each of said plurality of input signal buses characterized by: means responsive to a signal provided on one of said set of output lines for inhibiting a signal from being applied to one of said plurality of input signal buses.
Claim 2
Dependent Claim
79 words
A code translator circuit having a set of output lines and a plurality of input signal buses in which a different predetermined coded signal is provided on said set of output lines in response to a signal applied to each of said plurality of input signal buses characterized by: means responsive to a signal provided on one of said set of output lines for inhibiting a signal from being applied to one of said plurality of input signal buses.
Claim 3
Dependent Claim
143 words
A code-translating circuit responsive to a plurality of coded input signals which exhibits a predetermined priority for providing coded output signals including: first, second, third and fourth means for providing first, second, third and fourth signals in response to first, second, third and fourth signals in response to first, second, third and fourth coded input signals respectively; means responsive to said fourth signal for providing a digit signal to first and second output lines; means responsive to said third signal for providing said digit signal to said first output line; means responsive to said second signal for providing said digit signal to said second output line; means responsive to said digit signal on said first output line for inhibiting said first and second signals; and means responsive to said digit signal on said second output line for inhibiting said first and third signals.
Claim 4
Dependent Claim
143 words
A code-translating circuit responsive to a plurality of coded input signals which exhibits a predetermined priority for providing coded output signals including: first, second, third and fourth means for providing first, second, third and fourth signals in response to first, second, third and fourth signals in response to first, second, third and fourth coded input signals respectively; means responsive to said fourth signal for providing a digit signal to first and second output lines; means responsive to said third signal for providing said digit signal to said first output line; means responsive to said second signal for providing said digit signal to said second output line; means responsive to said digit signal on said first output line for inhibiting said first and second signals; and means responsive to said digit signal on said second output line for inhibiting said first and third signals.
Claim 5
Dependent Claim
23 words
The code-translating circuit as defined in claim 2 in which said first, second, third and fourth signal providing means are input signal buses.
Claim 6
Dependent Claim
26 words
The code-translating circuit as defined in claim 2 also including: means responsive to either said first, second, third, or fourth signals for providing a transfer signal.
Claim 7
Dependent Claim
71 words
The code-translating circuit as defined in claim 4 wherein: said means for inhibiting said second signal includes means for loading said second signal with a first impedance value; and said means for inhibiting said third signal includes means for loading said third signal with a second impedance value, said second impedance value being higher than said first impedance value so that said third signal will have priority over said second signal.
Claim 8
Dependent Claim
26 words
The code-translating circuit as defined in claim 4 also including: means responsive to said transfer signal for utilizing signals on said first and second output lines.
Claim 9
Dependent Claim
130 words
In combination: first and second code-translating circuits each of said code-translating circuits having a set of output lines and a plurality of input signal buses for providing a different predetermined coded signal on said set of output lines in response to a signal applied to each of said plurality of input signal buses; each of said code translator circuit also providing a transfer signal in response to actuation of any of said input signal buses; means for connecting each said set of output lines of said first code translator circuit to a corresponding one of said output lines of said second code translator circuit; a third code translator circuit; and means for applying said transfer signal from said first and second code translator circuits to said third code translator circuit.
Claim 10
Dependent Claim
130 words
In combination: first and second code-translating circuits each of said code-translating circuits having a set of output lines and a plurality of input signal buses for providing a different predetermined coded signal on said set of output lines in response to a signal applied to each of said plurality of input signal buses; each of said code translator circuit also providing a transfer signal in response to actuation of any of said input signal buses; means for connecting each said set of output lines of said first code translator circuit to a corresponding one of said output lines of said second code translator circuit; a third code translator circuit; and means for applying said transfer signal from said first and second code translator circuits to said third code translator circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |