US3609560A
Expired / Lapsed
US
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Data separation circuit for magnetic recorder memories
Assignee: BEDFORD ASSOCIATES Inc
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Filing: 1970-01-09
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Granted: 1971-09-28
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Expires: 1990-01-09
Abstract
Abstract A data separation circuit providing an output separation gate signal having a frequency proportional to the average frequency of the input clock pulse signals that are recorded on a magnetic rotating memory disc. The clock pulse signals are then readily separated from data pulse signals in the recorded signal even though the exact position in time of each pulse has been altered by the recording process. The data separation circuit comprises simple, easily assembled circuitry that tracks recording frequencies read from two types of magnetic rotating memory drives, one of which records at twice the frequency of the other. A major component of the data separation circuit is a frequency controllable oscillator that simultaneously produces a sawtooth wave and a clock pulse. The oscillator clock pulse rate is compared with the input recorded clock pulse rate and the comparator output is used to control the oscillator''s frequency rate. The separation gate signal is initiated and terminated when the frequency controlled sawtooth wave attains predetermined levels. Similarly, the attainment of a predetermined level by the sawtooth wave is used in generating the feedback signal to the oscillator when operating with a high frequency memory drive. Expensive and complicated high frequency pulse logic circuits are therefore not required.
Inventors
- 👤 Michael P Greenberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:05
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
133 words
Apparatus for generating a separation gate signal for separating data and clock signals from a combined signal subject to timing errors comprising: A. an oscillator a. producing a sawtooth signal and b. producing a second pulse signal, 1. said first and second signals being synchronized and occurring at a controllable frequency rate, and said oscillator being c. responsive to an input signal to control said frequency rate; B. first means a. responsive to said sawtooth signal attaining a first predetermined value to initiate the separation gate signal; and b. responsive to said sawtooth signal attaining a second predetermined value to terminate the separation gate signal; and C. second means a. for comparing the frequency rate of said oscillator with the frequency rate of the clock signals; and b. for producing said input signal.
Claim 2
Dependent Claim
133 words
Apparatus for generating a separation gate signal for separating data and clock signals from a combined signal subject to timing errors comprising: A. an oscillator a. producing a sawtooth signal and b. producing a second pulse signal, 1. said first and second signals being synchronized and occurring at a controllable frequency rate, and said oscillator being c. responsive to an input signal to control said frequency rate; B. first means a. responsive to said sawtooth signal attaining a first predetermined value to initiate the separation gate signal; and b. responsive to said sawtooth signal attaining a second predetermined value to terminate the separation gate signal; and C. second means a. for comparing the frequency rate of said oscillator with the frequency rate of the clock signals; and b. for producing said input signal.
Claim 3
Dependent Claim
24 words
Apparatus as defined in claim 1 wherein said first means comprises: c. a first and second comparator circuit and a separation gate flip-flop circuit,
Claim 4
Dependent Claim
71 words
responsive to the leading edge of signal (A) to initiate said output signal in the opposite polarity and responsive to the leading edge of signal (B) to terminate said output signal, and further responsive to the trailing edge of signal (A) to initiate said output signal in the opposite polarity and responsive to the trailing edge of signal (B) to terminate said output signal, when signal (B) is trailing signal (A).
Claim 5
Dependent Claim
71 words
responsive to the leading edge of signal (A) to initiate said output signal in the opposite polarity and responsive to the leading edge of signal (B) to terminate said output signal, and further responsive to the trailing edge of signal (A) to initiate said output signal in the opposite polarity and responsive to the trailing edge of signal (B) to terminate said output signal, when signal (B) is trailing signal (A).
Claim 6
Dependent Claim
168 words
Apparatus as defined in claim 1 wherein said second means comprises: c. a first flip-flop responsive to said second pulse signal to set its state to produce a state indicating output signal (A), d. a second flip-flop adapted to respond to the separated clock signal to change its state and producing a state indicating output signal (B), e. a comparator circuit responsive to said sawtooth signal attaining a predetermined value to produce an output signal, f. a third flip-flop responsive to said comparator circuit output signal to set its state to produce a state indicating output signal (C), if said first flip-flop is in state (A) and produce a state indicating output signal (C) if said first flip-flop is in state (A), g. logic means responsive to signals (A), (B) and (C) to produce a first output signal of a first polarity when the logical expression (A.B.C) v (A.B.C) is true and second output signal oF a second polarity when the logical expression (A.B.C) v (A.B.C) is true.
Claim 7
Dependent Claim
55 words
Apparatus as defined in claim 3, further defined in that said input signal to said oscillator is an electrical current and said second means further comprises: h. a controlled-current source connected to supply said oscillator input signal, and i. a low-pass filter through which said logic means output signal is supplied to said controlled-current source.
Claim 8
Dependent Claim
7 words
Apparatus as defined in claim 3, wherein:
Claim 9
Dependent Claim
11 words
Apparatus as defined in claim 3 wherein said logic means is:
Claim 10
Dependent Claim
38 words
Apparatus for generating a separation gate signal for separating data and clock signals from a combined signal subject to timing error comprising: A. an oscillator a. producing a first sawtooth signal, and b. producing a second pulse signal,
Claim 11
Dependent Claim
38 words
Apparatus for generating a separation gate signal for separating data and clock signals from a combined signal subject to timing error comprising: A. an oscillator a. producing a first sawtooth signal, and b. producing a second pulse signal,
Claim 12
Dependent Claim
27 words
Apparatus as defined in claim 7, wherein said first means comprises a comparator circuit to produce said clock signal when said sawtooth signal attains a predetermined value.
Claim 13
Dependent Claim
166 words
Apparatus as defined in claim 7, wherein said second means comprises: a. a first flip-flop responsive to said second pulse signal to set its state to produce a state indicating output signal (A), b. a second flip-flop adapted to respond to the separated clock signal to change its state and produce a state indicating output signal (B), c. logic control means responsive to said pulse signal to produce an output signal, d. a third flip-flop responsive to said logic control means output signal to set its state to produce a state indicating output signal (C) if said first flip-flop is in state (A) and produce a state indicating output signal (C) if said first flip-flop is in state (A). e. logic means responsive to signals (A), (B) and (C) to produce a first output signal of a first polarity when the logic expression (A.B.C) v (A.B.C) is true and a second output signal of a second polArity when the logical expression (A.B.C) v (A.B.C) is true.
Claim 14
Dependent Claim
46 words
Apparatus as defined in claim 7, wherein said first logic means is further defined as being responsive to signals (A) and (C) to produce an output signal defined by the logic equation (A.C) v (A.C) which is supplied to said data terminal of said flip-flop circuit.
Claim 15
Dependent Claim
58 words
Apparatus as defined in claim 9, wherein said second means is further defined in that said input signal is an electrical current and said second means further comprises: f. a controlled-current source connected to supply said oscillator input signal, and g. a low-pass filter through which said logical means output signal is supplied to control said controlled-current source.
Claim 16
Dependent Claim
61 words
Apparatus as defined in claim 9, wherein said second means is further defined in that said first flip-flop is responsive to said second pulse signal to set its state to produce a state indicating output signal (A) if said third flip-flop is in state (C) and produce a state indicating output signal (A) if said third flip-flop is in state (C).
Claim 17
Dependent Claim
15 words
Apparatus as defined in claim 9, wherein said logic means is further defined as being;
Claim 18
Dependent Claim
38 words
Apparatus for generating a separation gate signal for separating data and clock signals from a combined signal subject to timing errors comprising: A. an oscillator a. producing a first sawtooth signal, and b. producing a second pulse signal,
Claim 19
Dependent Claim
38 words
Apparatus for generating a separation gate signal for separating data and clock signals from a combined signal subject to timing errors comprising: A. an oscillator a. producing a first sawtooth signal, and b. producing a second pulse signal,
Claim 20
Dependent Claim
180 words
Apparatus as defined in claiM 14 wherein said last means further comprises: d. a first flip-flop responsive to said second pulse signal to set its state to produce a state indicating output signal (A), e. a second flip-flop adapted to respond to the separated clock signal to change its state and produce a state indicating output signal (B), f. logic control means responsive to said third comparator circuit depending upon the frequency mode selected responsive to said second pulse signal to produce an output signal, g. a third flip-flop responsive to said third comparator circuit output signal to set its state to produce a state indicating output signal (C) if said first flip-flop is in state (A) and produce a state indicating output signal (C) if said first flip-flop is in state (A). h. logic means responsive to signals (A), (B) and (C) to produce a first output signal of a first polarity when the logical expression (A.B.C) v (A.B.C) is true and a second output signal of a second polarity when the logical expression (A.B.C) v (A.B.C) is true.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |