US3609405A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sharp rise-and-fall time,high-amplitude pulse generator
Assignee: Lockheed Martin Tactical Systems Inc
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Filing: 1969-02-03
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Granted: 1971-09-28
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Expires: 1989-02-03
Abstract
Abstract A pulse circuit switches in response to a bipolar digital logic input pulse to provide a sequential on-drive off-drive current thru low-impedance charge and discharge paths to drive an output semiconductor circuit. The output semiconductor circuit responds to the on-drive off-drive current and switches to provide a lowimpedance charge path for a high-amplitude, high-speed output current pulse.
Inventors
- 👤 Jon M Surprise
- 👤 Charles D Blust
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:46
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/12; H03K5/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
283 words
A pulse-switching circuit comprising: a. a reference voltage source; b. a source of logic pulses bipolar with respect to the reference voltage source; c. bias voltage means; d. first pair semiconductor means having base, emitter, and collector electrodes, one of the pair base connected to the source of logic pulses, the other of the pair base connected to the reference voltage source, the collectors of the pair connected to the bias voltage means, and the pair interconnected at their emitters and to the bias voltage means wherein a current is effected to flow in one of the pair when the logic pulse is positive with respect to the reference voltage, and in the other of the pair when the logic pulse is negative with respect to the reference voltage; e. second pair semiconductor means having base, emitter, and collector electrodes, one of the pair having its collector connected to the bias voltage means and its Base connected to the collector of one of the first pair semiconductor means while the other of the pair is common-emitter connected and has its base connected to the collector of the other of said first semiconductor means, said second pair semiconductor means interconnected at the remaining emitter-collector electrodes to effect an on-drive off-drive output current at said interconnection in response to the alternate and sequential current flow in the first pair semiconductor means; and f. output semiconductor means having base, emitter, and collector electrodes, said means base connected to the emitter collector interconnection of the second pair semiconductor means and responsive to the on-drive off-drive output of the second pair semiconductor means, and the collector-emitter circuit biased to provide high-speed, high-amplitude current pulses when switched into conduction.
Claim 2
Dependent Claim
283 words
A pulse-switching circuit comprising: a. a reference voltage source; b. a source of logic pulses bipolar with respect to the reference voltage source; c. bias voltage means; d. first pair semiconductor means having base, emitter, and collector electrodes, one of the pair base connected to the source of logic pulses, the other of the pair base connected to the reference voltage source, the collectors of the pair connected to the bias voltage means, and the pair interconnected at their emitters and to the bias voltage means wherein a current is effected to flow in one of the pair when the logic pulse is positive with respect to the reference voltage, and in the other of the pair when the logic pulse is negative with respect to the reference voltage; e. second pair semiconductor means having base, emitter, and collector electrodes, one of the pair having its collector connected to the bias voltage means and its Base connected to the collector of one of the first pair semiconductor means while the other of the pair is common-emitter connected and has its base connected to the collector of the other of said first semiconductor means, said second pair semiconductor means interconnected at the remaining emitter-collector electrodes to effect an on-drive off-drive output current at said interconnection in response to the alternate and sequential current flow in the first pair semiconductor means; and f. output semiconductor means having base, emitter, and collector electrodes, said means base connected to the emitter collector interconnection of the second pair semiconductor means and responsive to the on-drive off-drive output of the second pair semiconductor means, and the collector-emitter circuit biased to provide high-speed, high-amplitude current pulses when switched into conduction.
Claim 3
Dependent Claim
19 words
The switching circuit of claim 1 wherein the output semiconductor means is an NPN-type transistor in a common-emitter configuration.
Claim 4
Dependent Claim
61 words
The switching circuit of claim 1 wherein: a. the output semiconductor means is a PNP-type transistor; and b. a capacitor couples the base of said transistor to the emitter-collector interconnection of the second pair semiconductor means and which capacitor responds to the on-drive off-drive current of said second pair semiconductor means to drive the output semiconductor into either cutoff or conduction.
Claim 5
Dependent Claim
261 words
A switching circuit comprising in combination, four transistors of like conductivity type and an output transistor each having base, emitter, and collector electrodes, a source of collector emitter bias voltage, a source of reference voltage, a source of bipolar input pulses, means coupling the base of a first of said transistors to the source of reference voltage, means coupling the base of a second of said transistors to the source of bipolar input pulses, means coupling the collectors of said first and second transistors to the bias voltage, means intercoupling the emitters of said first and second transistors so that they operate as an emitter coupled pair wherein current flows in one of the pair when the input is positive with respect to the reference voltage and in the other of the pair when the input is negative with respect to the reference voltage, means coupling the base of a third of said transistors to the collector of said second transistor, said third transistor in a common emitter configuration, means coupling the base of the fourth of said transistors to the collector of said first transistor, means coupling the collector of said fourth transistor to the bias voltage, means coupling the base of said output transistor to the collector of said third transistor and to the emitter of said fourth transistor such that said output transistor is driven into either of its conductivity states by the switching of the third and fourth transistors, said output transistor having its collector emitter circuit biased to provide high-speed, high-amplitude pulses to an output terminal.
Claim 6
Dependent Claim
261 words
A switching circuit comprising in combination, four transistors of like conductivity type and an output transistor each having base, emitter, and collector electrodes, a source of collector emitter bias voltage, a source of reference voltage, a source of bipolar input pulses, means coupling the base of a first of said transistors to the source of reference voltage, means coupling the base of a second of said transistors to the source of bipolar input pulses, means coupling the collectors of said first and second transistors to the bias voltage, means intercoupling the emitters of said first and second transistors so that they operate as an emitter coupled pair wherein current flows in one of the pair when the input is positive with respect to the reference voltage and in the other of the pair when the input is negative with respect to the reference voltage, means coupling the base of a third of said transistors to the collector of said second transistor, said third transistor in a common emitter configuration, means coupling the base of the fourth of said transistors to the collector of said first transistor, means coupling the collector of said fourth transistor to the bias voltage, means coupling the base of said output transistor to the collector of said third transistor and to the emitter of said fourth transistor such that said output transistor is driven into either of its conductivity states by the switching of the third and fourth transistors, said output transistor having its collector emitter circuit biased to provide high-speed, high-amplitude pulses to an output terminal.
Claim 7
Dependent Claim
13 words
The circuit of claim 1 wherein the output transistor is an NPN-type semiconductor.
Claim 8
Dependent Claim
59 words
The circuit of claim 1 wherein the output transistor is a PNP-type semiconductor and a capacitor couples its base electrode to the emitter collector intercoupled third and fourth transistors to charge and discharge in response to the third and fourth transistor switching and providing on-drive off-drive current to drive the output transistor into either of its states of conductivity.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |