US3609398A
Expired / Lapsed
US
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High-speed integrated logic circuit
Assignee: Texas Instruments Inc
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Filing: 1968-12-31
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Granted: 1971-09-28
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Expires: 1988-12-31
Abstract
Abstract High-speed logic switching is accomplished by employing an antisaturation clamped, prebiased output stage in a logic circuit of transistors having a high internal cutoff frequency. An output transistor in a logic circuit is shunted between the base and collector electrodes with a clamping transistor which shunts excess base drive to the collector electrode, thus preventing saturation thereof. When in a nonamplification mode, the clamping transistor comprises part of a voltage divider network that prebiases the base electrode of the output amplifier. This divider network is connected to a reference voltage in a circuit including series-arranged diodes.
Inventors
- 👤 John William Kronlage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:35
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K19/00; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
250 words
An antisaturation, prebiased, a high-speed transistor logic circuit comprising: (a first) an output transistor having an emitter electrode at ground potential, a collector electrode connected to an output terminal and to a supply voltage through an output resistor, and (including) a base electrode connected to ground potential through a prebiasing resistor, a drive source coupled to the base electrode of said output transistor for supplying driving current to control conduction through said (first) output transistor, a (second) clamping transistor having its emitter and collector electrodes (including a base collector diode with the collector electrode) respectively connected to the collector and base of electrodes of said output transistor, a series-connected pair of PN junction devices coupled between said supply voltage and ground potential to provide a fixedvoltage terminal; wherein said clamping transistor has its base terminal coupled to said fixed voltage terminal through a biasing resistor for coupling a prebiasing voltage to the base terminal of said output transistor when said output transistor is in its OFF state, said prebiasing voltage being developed through a series circuit, including said fixed voltage terminal, said biasing resistor, the base-collector junction of said clamping transistor, and said prebiasing resistor; and wherein said output transistor is maintained below saturation when in its ON state by a series circuit including the base terminal of said output transistor, the collector terminal of said clamping transistor, the collector-emitter junction of said clamping transistor, the emitter terminal of said clamping transistor, and the collector terminal of said output transistor.
Claim 2
Dependent Claim
250 words
An antisaturation, prebiased, a high-speed transistor logic circuit comprising: (a first) an output transistor having an emitter electrode at ground potential, a collector electrode connected to an output terminal and to a supply voltage through an output resistor, and (including) a base electrode connected to ground potential through a prebiasing resistor, a drive source coupled to the base electrode of said output transistor for supplying driving current to control conduction through said (first) output transistor, a (second) clamping transistor having its emitter and collector electrodes (including a base collector diode with the collector electrode) respectively connected to the collector and base of electrodes of said output transistor, a series-connected pair of PN junction devices coupled between said supply voltage and ground potential to provide a fixedvoltage terminal; wherein said clamping transistor has its base terminal coupled to said fixed voltage terminal through a biasing resistor for coupling a prebiasing voltage to the base terminal of said output transistor when said output transistor is in its OFF state, said prebiasing voltage being developed through a series circuit, including said fixed voltage terminal, said biasing resistor, the base-collector junction of said clamping transistor, and said prebiasing resistor; and wherein said output transistor is maintained below saturation when in its ON state by a series circuit including the base terminal of said output transistor, the collector terminal of said clamping transistor, the collector-emitter junction of said clamping transistor, the emitter terminal of said clamping transistor, and the collector terminal of said output transistor.
Claim 3
Dependent Claim
159 words
An antisaturation, prebiased, high-speed transistor logic circuit as set forth in claim 1 wherein said drive source includes: a first drive transistor having a collector electrode, coupled to said supply voltage, a base electrode, and an emitter electrode connected to the base electrode of said (first) output transistor and to said (second) prebiasing resistor, a second clamping transistor having a base electrode, an emitter electrode coupled (tiEd) to the collector electrode of said first drive transistor and a collector electrode coupled to the base electrode of said first drive transistor for clamping the collector electrode thereof at a fixed level above the emitter electrode thereof when said first drive transistor operates in an amplification mode, and an input transistor having a base electrode coupled to the base electrode of said second clamping transistor, a collector electrode coupled (tied) to the base electrode of said first drive transistor, and an emitter electrode connected to (a signal source) an input terminal.
Claim 4
Dependent Claim
53 words
An antisaturation, prebiased, a high-speed, transistor logic circuit as set forth in claim 2, wherein said (voltage source comprises) PN junction devices are first and second diodes coupled in series (to the first) with said biasing resistor and (a direct current) said supply voltage for providing said prebiasing voltage to said output transistor.
Claim 5
Dependent Claim
76 words
An antisaturation, prebiased, a high-speed, transistor logic circuit as set forth in claim 2 wherein said (voltage source includes) PN junction devices are first and second transistors, with the emitter-base (diode) circuit of (the) said first transistor and the collector base (diode) circuit of (the) said second transistor (are) interconnected in series (to the first) with said biasing resistor (to provide a) and said ground potential for providing temperature-compensated prebias to (the first) said output transistor.
Claim 6
Dependent Claim
219 words
An antisaturation, prebiased transistor logic switch, comprising in combination: a. an output transistor having a collector terminal coupled to a supply voltage, through an output resistor, an emitter terminal coupled to a reference voltage, and a base terminal coupled to a signal source and to said reference voltage through a prebiasing resistor; b. a clamping transistor having its emitter and collector terminals respectively coupled to the collector and base terminals of said output transistor; c. a series-connected resistor-diode circuit coupled between said supply voltage and said reference voltage to provide a fixed voltage terminal; wherein d. said clamping transistor has its base terminal coupled to said fixed voltage terminal through a biasing resistor for coupling a prebiasing voltage to the base terminal of said output transistor when said output transistor is in its OFF state, said prebiasing voltage being developed through a series circuit including said fixed voltage terminal, said biasing resistor, the base-collector junction of said clamping transistor, and said prebiasing resistor; and wherein e. said output transistor is maintained below saturation when in its ON state by a series circuit including the base terminal of said output transistor, the collector terminal of said clamping transistor, the collector-emitter junction of said clamping transistor, the emitter terminal of said clamping transistor, and the collector terminal of said output transistor.
Claim 7
Dependent Claim
219 words
An antisaturation, prebiased transistor logic switch, comprising in combination: a. an output transistor having a collector terminal coupled to a supply voltage, through an output resistor, an emitter terminal coupled to a reference voltage, and a base terminal coupled to a signal source and to said reference voltage through a prebiasing resistor; b. a clamping transistor having its emitter and collector terminals respectively coupled to the collector and base terminals of said output transistor; c. a series-connected resistor-diode circuit coupled between said supply voltage and said reference voltage to provide a fixed voltage terminal; wherein d. said clamping transistor has its base terminal coupled to said fixed voltage terminal through a biasing resistor for coupling a prebiasing voltage to the base terminal of said output transistor when said output transistor is in its OFF state, said prebiasing voltage being developed through a series circuit including said fixed voltage terminal, said biasing resistor, the base-collector junction of said clamping transistor, and said prebiasing resistor; and wherein e. said output transistor is maintained below saturation when in its ON state by a series circuit including the base terminal of said output transistor, the collector terminal of said clamping transistor, the collector-emitter junction of said clamping transistor, the emitter terminal of said clamping transistor, and the collector terminal of said output transistor.
Claim 8
Dependent Claim
32 words
An antisaturation, prebiased, transistor logic switch as set forth in claim 5 wherein said series-connected circuit includes a pair of series diodes connected between said fixed voltage terminal and said reference voltage.
Claim 9
Dependent Claim
49 words
An antisaturation, prebiased, transistor logic switch as set forth in claim 5 wherein said series-connected circuit includes first and second transistors, with the emitter-base junction of said first transistor and the collector-base junction of said second transistor interconnected in series between said fixed voltage terminal and said reference voltage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |