Conditional replenishment video system with variable length address code

Claim 2

A redundancy reduction transmission system comprising means for generating a plurality of first digital words each one of which has a value which indicates the sampled amplitude of an input signal, means for generating a plurality of second digital words each one of which has a value which indicates the position of its corresponding first digital word in a predetermined group of samples of said input signal, means for selecting one of said first digital words for transmission, and a memory means responsive to said selecting means for storing the selected one of said first digital words and its corresponding second digital word, characterized in that a means for reading out digital bits stored in said memory means couples all of the digital bits of the selected first digital word and selected bits of its corresponding second digital word to a digital transmitter, the selection of bits from said second digital word being based on the interval between the location of a previously transmitted first digital word in said group of samples and the end of said group.

Claim 3

A redundancy reduction transmission system as defined in claim 1 wherein said means for reading out digital bits stored in said memory means includes means responsive both to said means for selecting and to the second digital word corresponding to said selected first digital word for developing and storing a control word the value of which indicates the bits to be coupled to said digital transmitter from a subsequent second digital word corresponding to a next selected first digital word.

Claim 4

A redundancy reduction transmission system as defined in claim 2 wherein said means for reading out digital bits stored in said memory means includes a means responsive to said control word for selectively reading out the digital bits of the second digital word stored in said memory means.

Claim 5

A redundancy reduction transmission system as defined in claim 2 wherein said means for developing and storing a control word includes means for subtracting a predetermined value from said second digital word corresponding to said first digital word selected for transmission, means responsive to the output of said subtracting means for developing a digital control word having digital bits of one value both in the bit position having the most significant logical ''''1'''' at the output of said subtracting means and in lower valued bit positions, and a second memory means for storing the digital controL word developed by said means responsive to the output of said subtracting means.

Claim 6

A redundancy reduction transmission system as defined in claim 4 wherein said means for reading out digital bits stored in said first-mentioned memory means includes a means responsive to said digital control word for selectively reading out the digital bits of the second digital word stored in said first-mentioned memory means.

Claim 7

In a redundancy reduction system in which selected samples of an input signal are transmitted to a receiving location, apparatus for indicating the location of each transmitted sample within a predetermined group of samples comprising means for generating a digital address word for each sample the value of which word indicates the length of the interval between said each sample and the end of said group, means responsive to said address word for indicating the number of bits required to locate a subsequent sample in the interval between said each sample and the end of said group, and means responsive to said indicating means for selectively rejecting most significant bits in the address word corresponding to said subsequent sample.

Claim 8

In a redundancy reduction system in which selected samples of an input signal are transmitted to a receiving location, apparatus for indicating the location of each transmitted sample within a predetermined group of samples comprising means for generating a digital address word for each sample the value of which word indicates the length of the interval between said each sample and the end of said group, means responsive to said address word for indicating the number of bits required to locate a subsequent sample in the interval between said each sample and the end of said group, and means responsive to said indicating means for selectively rejecting most significant bits in the address word corresponding to said subsequent sample.

Claim 9

Apparatus as defined in claim 6 wherein said means for indicating the number of bits required to locate a subsequent sample includes means for subtracting a predetermined value from said digital address word to provide a lower valued address word, and means responsive to said lower valued address word for developing a control word having a digital bit of one value both in the same bit position as the most significant logical ''''1'''' in said lower valued address word and in all lower valued bit positions and having a digital bit of the opposite value in the remaining bit positions.

Claim 10

Apparatus as defined in claim 7 wherein said means for selectively rejecting most significant bits includes a memory means for storing said control word, and a means responsive to said memory means for selectively coupling only those bits of an address word which correspond to the bit positions in said control word having said digital bit of one value.

Claim 11

In a redundancy reduction system wherein each sample of an input signal is accompanied by an address word which indicates the position of its sample in a group of samples, apparatus for reducing the number of bits required to be transmitted for the purpose of addressing a sample selected for transmission comprising means for subtracting a predetermined value from a first address word to produce a lower valued word, means responsive to said lower valued word for generating a control word having a value which indicates the bit positions to be transmitted from a subsequent address word, means for storing said control word, and means responsive to said control word for selectively coupling bits from a subsequent address word to a digital transmitter.

Claim 12

In a redundancy reduction system wherein each sample of an input signal is accompanied by an address word which indicates the position of its sample in a group of samples, apparatus for reducing the number of bits required to be transmitted for the purpose of addressing a sample selected for transmission comprising means for subtracting a predetermined value from a first address word to produce a lower valued word, means responsive to said lower valued word for generating a control word having a value which indicates the bit positions to be transmitted from a subsequent address word, means for storing said control word, and means responsive to said control word for selectively coupling bits from a subsequent address word to a digital transmitter.

Claim 13

Apparatus as defined in claim 9 wherein said predetermined value is equal to one and said means for generating a control word includes means responsive to said lower valued word for providing a digital word having a digital bit of one value both in the bit position of said lower valued word having the most significant logical ''''1'''' and in lower valued bit positions.

Claim 14

Apparatus as defined in claim 10 wherein said means for selectively coupling bits from a subsequent address word includes a plurality of exclusive OR gates equal in number to one less than the number of bit positions in said control word.

Claim 15

Receiving apparatus in a redundancy reduction system for separating samples from a serial bit stream, each sample having an amplitude digital word preceded by an address digital word with a variable number of bits, a buffer memory means for storing said serial bit stream, a data shift register connected to said buffer memory means for receiving digital bits read out of said buffer memory means, data memory means for storing the digital bits present in said data shift register in response to a control signal at iTs clock input, means responsive to a digital word stored in predetermined areas of storage in said data memory means for generating said control signal, means responsive to said control signal for resetting said data shift register, and means responsive to the resetting of said data shift register for reading out a plurality of bits from said buffer memory means, the number of bits read out being a function of the digital word stored in said predetermined areas of storage in said data memory means.

Claim 16

Receiving apparatus in a redundancy reduction system for separating samples from a serial bit stream, each sample having an amplitude digital word preceded by an address digital word with a variable number of bits, a buffer memory means for storing said serial bit stream, a data shift register connected to said buffer memory means for receiving digital bits read out of said buffer memory means, data memory means for storing the digital bits present in said data shift register in response to a control signal at iTs clock input, means responsive to a digital word stored in predetermined areas of storage in said data memory means for generating said control signal, means responsive to said control signal for resetting said data shift register, and means responsive to the resetting of said data shift register for reading out a plurality of bits from said buffer memory means, the number of bits read out being a function of the digital word stored in said predetermined areas of storage in said data memory means.

Claim 17

In receiving redundancy reduction apparatus as defined in claim 12 wherein said means for reading out a plurality of bits from said buffer memory means includes means for subtracting a predetermined value from said digital word stored in said predetermined areas of storage to produce a lower valued digital word, and means responsive to the resetting of said data shift register for generating a plurality of voltage pulses, the number of pulses being determined by the value of said lower valued digital word.

Claim 18

Receiving apparatus in a redundancy reduction system for replenishing a frame memory with samples from a serial bit stream, each sample having an amplitude digital word preceded by an address digital word with a variable number of bits, a buffer memory means for storing said serial bit stream, a data shift register for receiving digital bits read out of said buffer memory means, data memory means for storing the digital bits present in said data shift register in response to a control signal at its clock input, an address generator for periodically providing a memory address digital word which indicates a position in said frame memory available for replenishment, means for generating said control signal when a match is obtained between said memory address digital word and the digital bits stored in predetermined areas of storage in said data memory means, means responsive to said control signal for resetting said data shift register, means responsive to the digital bits stored in said predetermined areas of storage in said data memory means for developing a control word the value of which indicates the number of bits present in the next sample to be coupled out of said buffer memory means, and means responsive to the resetting of said data shift register and to said control word for reading out the number of bits indicated by said control word from said buffer memory means.

Claim 19

Receiving apparatus in a redundancy reduction system for replenishing a frame memory with samples from a serial bit stream, each sample having an amplitude digital word preceded by an address digital word with a variable number of bits, a buffer memory means for storing said serial bit stream, a data shift register for receiving digital bits read out of said buffer memory means, data memory means for storing the digital bits present in said data shift register in response to a control signal at its clock input, an address generator for periodically providing a memory address digital word which indicates a position in said frame memory available for replenishment, means for generating said control signal when a match is obtained between said memory address digital word and the digital bits stored in predetermined areas of storage in said data memory means, means responsive to said control signal for resetting said data shift register, means responsive to the digital bits stored in said predetermined areas of storage in said data memory means for developing a control word the value of which indicates the number of bits present in the next sample to be coupled out of said buffer memory means, and means responsive to the resetting of said data shift register and to said control word for reading out the number of bits indicated by said control word from said buffer memory means.

Claim 20

Apparatus as defined in claim 14 wherein said means for developing a control word includes means for subtracting a predetermined value from the digital bits stored in said predetermined areas of storage.

Claim 21

Apparatus as defined in claim 15 wherein said means for reading out the number of bits indicated by said control word from said buffer memory means includes means for generating a plurality of voltage pulses, the number of pulses being determined by the value of said control word.