US3604911A
Expired / Lapsed
US
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Serial-parallel digital correlator
Assignee: GTE Sylvania Inc
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Filing: 1969-05-15
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Granted: 1971-09-14
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Expires: 1989-05-15
Abstract
Abstract A digital correlator for measuring the amount of agreement between two binary sequences comprising a plurality of cascadeconnected segment comparators each operative to serially compare the bits within an M-bit segment of the sequences. A summing bus collects in parallel the comparison output signals of the segment comparators and applies them to a detector comprising an integrator and threshold circuit. Each segment comparator comprises a pair of M-bit shift registers each of which processes bits of a respective one of the binary sequences, a pair of exclusive OR gates for controlling serial loading and recirculation of respective registers, clock drive and feedback connections for recirculating the contents of both registers between the loading of each bit into one of the registers, and a modulo 2 adder for serially comparing the outputs of the registers.
Inventors
- 👤 Joseph W Schmitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:34
CPC Classifications
G; G06; G06J; G06J1/00; G06J1/005
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A digital correlator for generating an output signal indicative of the amount of agreement between first and second binary sequences comprising, in combination, a plurality of cascade-connected segment comparators each of which is operative to store and serially compare the bits within a selected segment of said first and second binary sequences and to provide a serial comparison output signal, means for serially loading bits of said first and second binary sequences into said segment comparators, means for recirculating the bits stored in each of said segment comparators between the loading of each bit of said first sequence, means for collecting in parallel the serial comparison output signals of said segment comparators, and detector means operative in response to said collected comparison signals to provide a measure of the amount of agreement between said first and second binary sequences.
Claim 2
Dependent Claim
139 words
A digital correlator for generating an output signal indicative of the amount of agreement between first and second binary sequences comprising, in combination, a plurality of cascade-connected segment comparators each of which is operative to store and serially compare the bits within a selected segment of said first and second binary sequences and to provide a serial comparison output signal, means for serially loading bits of said first and second binary sequences into said segment comparators, means for recirculating the bits stored in each of said segment comparators between the loading of each bit of said first sequence, means for collecting in parallel the serial comparison output signals of said segment comparators, and detector means operative in response to said collected comparison signals to provide a measure of the amount of agreement between said first and second binary sequences.
Claim 3
Dependent Claim
96 words
A digital correlator in accordance with claim 1 wherein each of said segment comparators includes first and second shift registers and means for serially comparing the outputs of said first and second registers, said loading means includes means for serially loading bits of said first binary sequence into said first register and means for serially loading bits of said sEcond binary sequence into said second register, and said recirculating means includes means for recirculating the contents of said first and second registers between the loading of each bit of said first sequence into said first register.
Claim 4
Dependent Claim
31 words
A digital correlator in accordance with claim 2 wherein said serial comparison means comprises a modulo 2 adder having inputs connected to the serial outputs of said first and second registers.
Claim 5
Dependent Claim
82 words
A digital correlator in accordance with claim 3 wherein said means for loading said first register comprises a first logic circuit having an input connected to a source of said first binary sequence and an output connected to the serial input of said first register, and said means for loading said second register comprises a second logic circuit having an input connected to a source of said second binary sequence and an output connected to the serial input of said second register.
Claim 6
Dependent Claim
44 words
A digital correlator in accordance with claim 4 wherein said sources of first and second binary sequences for at least one of said segment comparators respectively comprise serial outputs of first and second shift registers in a preceding one of said cascaded segment comparators.
Claim 7
Dependent Claim
120 words
A digital correlator in accordance with claim 4 wherein said first and second registers each have M-stages, and said recirculating means includes a feedback connection from a serial output of said first register to an input of said first logic circuit, a feedback connection from a serial output of second register to an input of said second logic circuit, means for applying clock pulses to drive said first and second registers at a rate M+1 times the bit rate of said first binary sequence, and means for controlling said first and second logic circuits to enable the recirculating feedback inputs thereof and to inhibit the first and second binary sequence inputs thereof for a period of at least M-clock pulses.
Claim 8
Dependent Claim
63 words
A digital correlator in accordance with claim 6 wherein said control means for said first and second logic circuits is further operative to inhibit the feedback inputs thereof and to enable the binary sequence inputs thereof during the M+1 clock pulse, and said means for applying clock pulses is further operative to inhibit application of the M+1 clock pulse to said second register.
Claim 9
Dependent Claim
79 words
A digital correlator in accordance with claim 7 wherein said means for collecting the serial comparison output signals of said segment comparators comprises a summing bus connected to the output of the modulo 2 adder in each of said segment comparators, and said detector means comprises an integrator having an input to which said summing bus is connected, means for dumping said integrator during the M+1 clock pulse, and a threshold circuit connected to the output of said integrator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-13 | 1975-03-15 | 1975-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-13 | 1979-03-15 | 1979-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-13 | 1983-03-15 | 1983-09-14 | $7700.00 | Window Closed / Lapsed |