Parallel comparator with simultaneous carry generation and an analog output

Claim 2

An adding circuit for coded digital signals or the like, comprising switch means, an output circuit and bias means both connected to the switch means, said bias means controlling conduction of the switch means to determine presence or absence of an output in the output circuit, in accordance with the state of the bias means, said bias means including an input circuit having resistance means for limiting the contribution of the input circuit to the state of the bias means to two units when the input circuit is connected to a constant potential source, said bias means also including four drain circuits, one of which drain circuits has resistance means for limiting the contribution of the one drain circuit to the state of the bias means to two units, and the other three of which drain circuits have resistance means for limiting the contribution of the other three drain circuits to the state of the bias means to one unit apiece when signal input potentials are applied thereto.

Claim 3

An adding circuit for one stage of an adder of coded digital signals having a plurality of adder stages of different significance, each stage of the adder including a carry and a carry-not output circuit, comprising switch means, an output circuit connected to the switch means for providing an output when the switch means is in one of two alternative conditions tHereof, a signal input circuit for providing an input signal to the adding circuit, an augend and addend signal circuit for each of a pair of signals to be added for providing an augend and addend signal to the adding circuit, a carry signal circuit for providing a carry signal from the next least significant adding stage to the adding circuit and a carry-not signal circuit for providing a carry-not signal from the next most significant adding stage to the adding circuit and bias means connected between each of the input signal circuit, augend and addend signal circuits, carry signal circuit and carry-not signal circuit and the switch means for placing the switch means in the one condition to provide an output from the output circuit on occurrence of either the augend or addend signals to be added in the adding circuit without the other signals being present, a carry signal from the preceding adding circuit without the other signals being present and on the presence of all of the input, augend, addend, carry and carry-not signals.

Claim 4

An adding circuit for one stage of an adder of coded digital signals having a plurality of adder stages of different significance, each stage of the adder including a carry and a carry-not output circuit, comprising switch means, an output circuit connected to the switch means for providing an output when the switch means is in one of two alternative conditions tHereof, a signal input circuit for providing an input signal to the adding circuit, an augend and addend signal circuit for each of a pair of signals to be added for providing an augend and addend signal to the adding circuit, a carry signal circuit for providing a carry signal from the next least significant adding stage to the adding circuit and a carry-not signal circuit for providing a carry-not signal from the next most significant adding stage to the adding circuit and bias means connected between each of the input signal circuit, augend and addend signal circuits, carry signal circuit and carry-not signal circuit and the switch means for placing the switch means in the one condition to provide an output from the output circuit on occurrence of either the augend or addend signals to be added in the adding circuit without the other signals being present, a carry signal from the preceding adding circuit without the other signals being present and on the presence of all of the input, augend, addend, carry and carry-not signals.

Claim 5

Structure as set forth in claim 2, wherein the bias means includes means for weighting each of the input, augend, addend, carry and carry-not signals and the input signal and the carry-not signal are each provided twice the weight of each of the augend, addend and carry signals by the weighting means.

Claim 6

A parallel carry circuit for coded digital signals or the like, comprising switch means, an output circuit and bias means both connected to the switch means, said bias means controlling conduction of the switch means to determine presence or absence of an output in the output circuit in accordance with the state of the bias means, said bias means including a plurality of pairs of current drain circuits connected to each other and to the switch means with each current drain circuit within a pair of current drain circuits having resistance means therein for equalizing the contribution of each of the current drain circuits of each pair of current drain circuits to the state of the bias means and for limiting the contribution of each pair of current drain circuits to the state of the bias means to twice that of the pair of current drain circuits corresponding to the next lower significant position in the coded digital signals, said bias means also including a current input circuit connected between a source of constant potential and the switch means having resistance means for limiting the contribution of the input circuit to the state of the bias means to half of the contribution of all the current drain circuits with signals present thereon when the constant potential source is applied to the input circuit.

Claim 7

A parallel carry circuit for coded digital signals or the like, comprising switch means, an output circuit and bias means both connected to the switch means, said bias means controlling conduction of the switch means to determine presence or absence of an output in the output circuit in accordance with the state of the bias means, said bias means including a plurality of pairs of current drain circuits connected to each other and to the switch means with each current drain circuit within a pair of current drain circuits having resistance means therein for equalizing the contribution of each of the current drain circuits of each pair of current drain circuits to the state of the bias means and for limiting the contribution of each pair of current drain circuits to the state of the bias means to twice that of the pair of current drain circuits corresponding to the next lower significant position in the coded digital signals, said bias means also including a current input circuit connected between a source of constant potential and the switch means having resistance means for limiting the contribution of the input circuit to the state of the bias means to half of the contribution of all the current drain circuits with signals present thereon when the constant potential source is applied to the input circuit.

Claim 8

A parallel carry circuit for one stage of an adder of coded digital signals including addends and augends of different significance which adder includes a plurality of adder stages of different significance corresponding to the significance of addends augends, comprising switch means, an output circuit connected to the switch means for providing an output when the switch means is in one of two alternative conditions thereof, a plurality of pairs of signal input circuits for providing an input signal to the carry circuit from the addend and augend pairs at each place of significance equal to and lesser than the significance of the one stage of the adder and bias means connected between each of the pairs of signal input circuits and the switch means for placing the switch means in the one condition only in response to any combinations of augend and addend input conditions represented by locations on one side of the diagonal of a Karnaugh map.

Claim 9

A parallel carry circuit for one stage of an adder of coded digital signals including addends and augends of different significance which adder includes a plurality of adder stages of different significance corresponding to the significance of addends augends, comprising switch means, an output circuit connected to the switch means for providing an output when the switch means is in one of two alternative conditions thereof, a plurality of pairs of signal input circuits for providing an input signal to the carry circuit from the addend and augend pairs at each place of significance equal to and lesser than the significance of the one stage of the adder and bias means connected between each of the pairs of signal input circuits and the switch means for placing the switch means in the one condition only in response to any combinations of augend and addend input conditions represented by locations on one side of the diagonal of a Karnaugh map.

Claim 10

A comparator comprising input terminals having a plurality of significant positions for receiving coded, digital numbers to be compared, a single switch means adding circuit for each significant position of the numbers to be compared connected to receive an input from the terminals at the corresponding significant positions, a plurality of corresponding single switch means pArallel carry circuits for providing a carry signal in a related significant position and a carry-not signal for the preceding significant position which parallel carry circuits are connected to receive an input from the corresponding significant position terminals and at least some preceding significant position terminals and to simultaneously provide an output to the adding circuits, and means connected to receive the output signals from the adding circuits for providing an output representative of the comparison of the numbers received at the input terminals.

Claim 11

A comparator comprising input terminals having a plurality of significant positions for receiving coded, digital numbers to be compared, a single switch means adding circuit for each significant position of the numbers to be compared connected to receive an input from the terminals at the corresponding significant positions, a plurality of corresponding single switch means pArallel carry circuits for providing a carry signal in a related significant position and a carry-not signal for the preceding significant position which parallel carry circuits are connected to receive an input from the corresponding significant position terminals and at least some preceding significant position terminals and to simultaneously provide an output to the adding circuits, and means connected to receive the output signals from the adding circuits for providing an output representative of the comparison of the numbers received at the input terminals.

Claim 12

A comparator comprising a source of coded digital numbers to be compared having a plurality of significant positions, an adding circuit for each significant position of the numbers to be compared connected to the source of the numbers, a plurality of corresponding single switching elements connected between the source of coded digital numbers and the adding circuits to receive inputs from said source of coded digital numbers from at least one group of significant positions thereof and to receive an auxiliary carry function from another group of lesser significant positions for providing a carry signal to the adding circuits corresponding to the one group of significant positions in a switch time simultaneously.

Claim 13

A comparator comprising a source of coded digital numbers to be compared having a plurality of significant positions, an adding circuit for each significant position of the numbers to be compared connected to the source of the numbers, a plurality of corresponding single switching elements connected between the source of coded digital numbers and the adding circuits to receive inputs from said source of coded digital numbers from at least one group of significant positions thereof and to receive an auxiliary carry function from another group of lesser significant positions for providing a carry signal to the adding circuits corresponding to the one group of significant positions in a switch time simultaneously.

Claim 14

A comparator comprising a source of coded digital numbers to be compared including augend and addend pairs of different significance, an adding circuit for each significant position of the numbers to be compared, each having an output signal, a plurality of corresponding single switching elements connected to receive inputs from said source of coded digital numbers for providing a parallel carry signal to the corresponding adding circuits simultaneously and for providing a carry-not signal to the adding circuit in the preceding significant position of the numbers to be compared.

Claim 15

A comparator comprising a source of coded digital numbers to be compared including augend and addend pairs of different significance, an adding circuit for each significant position of the numbers to be compared, each having an output signal, a plurality of corresponding single switching elements connected to receive inputs from said source of coded digital numbers for providing a parallel carry signal to the corresponding adding circuits simultaneously and for providing a carry-not signal to the adding circuit in the preceding significant position of the numbers to be compared.

Claim 16

A comparator including two input register circuits for parallel receiving binary coded digital numbers to be compared, a plurality of adding circuits in stages corresponding to the significant positions of the numbers to be compared, each including a single semiconductor connected to receive the input signal from both input registers for a particular significant position in the numbers to be compared, a carry signal for the respective stage and a carry-not signal from the next stage, a plurality of parallel carry circuits including a single semiconductor for receiving input signals from each significant position in the input registers up to and including the particular significant position the respective stage is associated with and for providing a carry-not output signal to the preceding stage, an inverter for receiving the carry-not signal and providing a carry signal to the particular stage which the specific parallel carry circuit is associated with and an analog ladder for receiving the output from the plurality of adding circuits to provide an output representative of the comparison of the input numbers.

Claim 17

A comparator including two input register circuits for parallel receiving binary coded digital numbers to be compared, a plurality of adding circuits in stages corresponding to the significant positions of the numbers to be compared, each including a single semiconductor connected to receive the input signal from both input registers for a particular significant position in the numbers to be compared, a carry signal for the respective stage and a carry-not signal from the next stage, a plurality of parallel carry circuits including a single semiconductor for receiving input signals from each significant position in the input registers up to and including the particular significant position the respective stage is associated with and for providing a carry-not output signal to the preceding stage, an inverter for receiving the carry-not signal and providing a carry signal to the particular stage which the specific parallel carry circuit is associated with and an analog ladder for receiving the output from the plurality of adding circuits to provide an output representative of the comparison of the input numbers.

Claim 18

Structure as set forth in claim 9 wherein at least one of the parallel carry circuits is fed signals from the input register circuit only from the significant position associated with the respective carry circuit and a carry signal from the preceding stage.

Claim 19

Structure as set forth in claim 9 and further including an inverter connected between the adding circuit of the most significant digit stage of the comparator and the most significant digit stage of the analog ladder whereby the output from the analog ladder is in both directions about a zero output.

Claim 20

Structure as set forth in claim 9 wherein at lease some of the parallel carry circuits are fed signals from the input register circuits only after a predetermined significant position of the numbers to be compared and are also fed a single carry signal from the stage preceding the predetermined significant position.

Claim 21

A comparator including a plurality of adder stages, a plurality of carry stages connected to the addEr stages, an analog ladder for providing an alternating current output from said comparator having a plurality of significant positions and a single capacitor connected between each adder stage and each significant position of the ladder for passing only alternating current signals to the ladder under control of the adder stages.

Claim 22

A comparator including a plurality of adder stages, a plurality of carry stages connected to the addEr stages, an analog ladder for providing an alternating current output from said comparator having a plurality of significant positions and a single capacitor connected between each adder stage and each significant position of the ladder for passing only alternating current signals to the ladder under control of the adder stages.

Claim 23

Structure as set forth in claim 13 and further including a second capacitor connected in series with the first capacitor and a secondary winding of a transformer connected in series with the second capacitor.

Claim 24

Structure as set forth in claim 13 wherein all of the alternating current signals are equal and further including means for inverting the alternating current signal under the control of the most significant adder stage.

Claim 25

A comparator comprising a source of coded digital numbers to be compared, an adding circuit for each significant position of the numbers to be compared, each having an output signal, a plurality of corresponding single switching elements connected to receive inputs from said source of coded digital numbers and for providing a carry signal to the corresponding adding circuits and a carry not signal to the adding circuit in the preceding significant position of the numbers to be compared.

Claim 26

A comparator comprising a source of coded digital numbers to be compared, an adding circuit for each significant position of the numbers to be compared, each having an output signal, a plurality of corresponding single switching elements connected to receive inputs from said source of coded digital numbers and for providing a carry signal to the corresponding adding circuits and a carry not signal to the adding circuit in the preceding significant position of the numbers to be compared.

Claim 27

Structure as set forth in claim 16, and further including means connected to receive the output signals from the adding circuits for providing an analog output representative of the comparison.

Claim 28

The adder as defined in claim 16 wherein the input addend and augend signals utilize the noncomplemented form at all significant positions thereof.