None-ambiguous reading systems for analog-to-digital converters

Claim 1

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising m sets of n logical circuits, m being the number of said n-digits notation code disks, the l-th circuit of said logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+l) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said higher order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits of the set corresponding to said higher order code disk being supplied with said carry signals Cr and lo from the set of n logical circuits corresponding to said lower order code disk, each of said logical circuits comprising a first NOR circuit coupled to said l, Cr and l-1 input terminals, a second NOR circuit coupled to said l, Cr and lo input terminals, a third NOR circuit coupled to said l, lo and l+1 input terminals, and an OR circuit coupled to said first, second and third NOR circuits.

Claim 2

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising m sets of n logical circuits, m being the number of said n-digits notation code disks, the l-th circuit of said logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+l) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said higher order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits of the set corresponding to said higher order code disk being supplied with said carry signals Cr and lo from the set of n logical circuits corresponding to said lower order code disk, each of said logical circuits comprising a first NOR circuit coupled to said l, Cr and l-1 input terminals, a second NOR circuit coupled to said l, Cr and lo input terminals, a third NOR circuit coupled to said l, lo and l+1 input terminals, and an OR circuit coupled to said first, second and third NOR circuits.

Claim 3

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising m sets of n logical circuits, m being the number of said n-digits notation code disks, the l-th circuit of said n logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+1) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears, and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said higher order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits of the set corresponding to said higher order code disk being supplied with said carry signals Cr and lo from the set of n logical circuits corresponding to said lower order code disk, each of said logical circuits comprising a first NAND circuit coupled to said l, Cr and l-1 input terminals, a second NAND circuit coupled to said l, Cr and lo input terminals, a third NAND circuit coupled to said l, lo and l+1 input terminals, and a fourth NAND circuit coupled to said first, second and third NAND circuits.

Claim 4

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising m sets of n logical circuits, m being the number of said n-digits notation code disks, the l-th circuit of said n logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+1) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears, and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said higher order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits of the set corresponding to said higher order code disk being supplied with said carry signals Cr and lo from the set of n logical circuits corresponding to said lower order code disk, each of said logical circuits comprising a first NAND circuit coupled to said l, Cr and l-1 input terminals, a second NAND circuit coupled to said l, Cr and lo input terminals, a third NAND circuit coupled to said l, lo and l+1 input terminals, and a fourth NAND circuit coupled to said first, second and third NAND circuits.

Claim 5

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising m sets of n logical circuits, m being the number of said n-digits notation code disks, the l-th circuit of said n logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+1) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears, and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said higher order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits of the set corresponding to said higher order code disk being supplied with said carry signals Cr and lo from the set of n logical circuits corresponding to said lower order code disk, each of said logical circuits comprising a first AND circuit coupled to said l, Cr and l-1 input terminals, a second AND circuit coupled to said l, Cr and lo input terminals, a third AND circuit coupled to said l, lo and l+1 input terminals, and an OR circuit coupled to said first, second and third AND circuits.

Claim 6

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising m sets of n logical circuits, m being the number of said n-digits notation code disks, the l-th circuit of said n logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+1) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears, and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said higher order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits of the set corresponding to said higher order code disk being supplied with said carry signals Cr and lo from the set of n logical circuits corresponding to said lower order code disk, each of said logical circuits comprising a first AND circuit coupled to said l, Cr and l-1 input terminals, a second AND circuit coupled to said l, Cr and lo input terminals, a third AND circuit coupled to said l, lo and l+1 input terminals, and an OR circuit coupled to said first, second and third AND circuits.

Claim 7

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising a set of n logical circuits, a delay circuit and a switching circuit, the l-th circuit of said n logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+1) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears, and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said high order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits being supplied with said carry signals Cr and lo from said L output terminal through said delay circuit, said switching circuit switching connections from said input terminals to said code disks from one code disk to another code disks with predetermined time intervals.

Claim 8

A system for reading digits from an analog-to-digital converter having at least two n-digits notation code disks, n being larger than two, said system comprising a set of n logical circuits, a delay circuit and a switching circuit, the l-th circuit of said n logical circuits performing the logical operation L l.(Cr.l-1+ Cr.l0+ lo.l+1) where L is the signal corresponding to any digit signal l generated from the higher order code disk of successive two code disks of said at least two n-digits notation code disks, Cr is a carry signal generated when one signal included in the upper group of output signals from the lower order code disk of said two code disks appears, and lo is a carry signal generated when one signal included in the lower group of outputs from said lower order code disk appears, said outputs of said lower code disk being divided into said upper and lower groups, said l-th logical circuit having Cr and lo input terminals for respectively receiving said carry signals Cr and lo from said lower code disk and l-1, l and l+1 input terminals for respectively receiving three successive digit signals l-1, l and l+1 from said high order code disk and L output terminal for deriving therefrom said signal corresponding to said digit signal l, said Cr and lo input terminals of each of said n logical circuits being supplied with said carry signals Cr and lo from said L output terminal through said delay circuit, said switching circuit switching connections from said input terminals to said code disks from one code disk to another code disks with predetermined time intervals.