US3603866A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Energizing system with digital control circuit for regulating multiphase inverter
Assignee: York International Corp
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Filing: 1970-03-24
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Granted: 1971-09-07
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Expires: 1990-03-24
Abstract
Abstract A two-phase electrical motor is driven by two separate inverter circuits under the regulation of a digital control circuit which provides and maintains a phase displacement between the inverter output voltages by utilizing a countdown circuit in connection with a basic clock circuit. The inverter AC output voltages include a plurality of pulses of the same polarity in each halfcycle to provide a resultant AC output voltage related to the clock frequency by another countdown circuit. Pulse duration is controlled to regulate the effective amplitude of the resultant AC output voltages. A chopper circuit prevents voltage swings in a varying DC supply from occurring in the DC input voltage which energizes the inverter circuits.
Inventors
- 👤 Kenneth E Opal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:24
CPC Classifications
H; H02; H02P; H02P27/00; H02P27/04; H02P27/06; H02P27/08; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/505; H02M7/515; H02M7/525; H02M7/527
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
209 words
A system for energizing first and second AC loads from a DC input voltage by providing first and second resultant AC output voltages displaced in phase from each other, each resultant AC output voltage having a plurality of pulses in each half-cycle, which system comprises: a first inverter circuit, connected for energization by the DC input voltage, including four controllable semiconductor switches connected to regulate both the direction and the level of current flow through the first AC load as different pairs of the semiconductor switches are rendered conductive; a second inverter circuit, connected for energization by the DC input voltage, including four additional controllable semiconductor switches connected to regulate both the direction and the level of current flow through the second AC load as different pairs of the semiconductor switches in the second inverter circuit are rendered conductive; and a digital control circuit, connected to control the times of conduction of the controllable semiconductor switches, including first and second countdown circuits, the first countdown circuit being connected to determine the number of pulses in each half-cycle of the resultant AC output voltages, and the second countdown circuit being connected to maintain the resultant AC output voltages displaced in phase with respect to each other by a predetermined amount.
Claim 2
Independent Claim
209 words
A system for energizing first and second AC loads from a DC input voltage by providing first and second resultant AC output voltages displaced in phase from each other, each resultant AC output voltage having a plurality of pulses in each half-cycle, which system comprises: a first inverter circuit, connected for energization by the DC input voltage, including four controllable semiconductor switches connected to regulate both the direction and the level of current flow through the first AC load as different pairs of the semiconductor switches are rendered conductive; a second inverter circuit, connected for energization by the DC input voltage, including four additional controllable semiconductor switches connected to regulate both the direction and the level of current flow through the second AC load as different pairs of the semiconductor switches in the second inverter circuit are rendered conductive; and a digital control circuit, connected to control the times of conduction of the controllable semiconductor switches, including first and second countdown circuits, the first countdown circuit being connected to determine the number of pulses in each half-cycle of the resultant AC output voltages, and the second countdown circuit being connected to maintain the resultant AC output voltages displaced in phase with respect to each other by a predetermined amount.
Claim 3
Dependent Claim
146 words
An energizing system as claimed in claim 1, in which said digital control circuit includes a clock circuit connected to provide a train of timing pulses for application to said first and second countdown circuits, a first flip-flop circuit coupled to said first countdown circuit and to two of the four controllable semiconductor switches in the first inverter circuit to provide first trigger pulses of a duration approximating a half-cycle of the resultant AC output voltages, and a second flip-flop circuit connected for regulation by said second countdown circuit and by said first flip-flop circuit, to provide second trigger pulses to two of the four controllable semiconductor switches in the second inverter circuit, which second trigger pulses are approximately equal in time duration but displaced in phase relative to the first trigger pulses, the extent of the phase displacement being determined by said second countdown circuit.
Claim 4
Dependent Claim
80 words
An energizing system as claimed in claim 2, in which said digital control circuit further includes a delay circuit connected to provide trigger pulses delayed in time relative to said timing pulses for application to those controllable semiconductor switches in the first and second inverter circuits which do not receive trigger pulses from either of the first and second flip-flop circuits, and means for adjusting the extent of the time delay between the delayed trigger pulses and the timing pulses.
Claim 5
Dependent Claim
44 words
An energizing system as claimed in claim 1, and further comprising a DC-to-DC converter circuit, coupled between a DC input circuit and said first and second inverter circuits, to prevent wide voltage swings in the DC input circuit from appearing in the inverter circuits.
Claim 6
Dependent Claim
31 words
An energizing system as claimed in claim 1, in which said first and second AC loads are the windings of a two-phase AC motor which is coupled to a mechanical load.
Claim 7
Independent Claim
226 words
A system for energizing first and second AC loads from a DC input voltage by providing first and second composite AC output voltages displaced in phase relative to each other, each composite AC output voltage having a plurality of pulses in each half-cycle, which system comprises: a first inverter connected for energization by the DC input voltage, including four controllable semiconductor switches connected to regulate both the direction and the level of current flow through the first AC load as different pairs of the semiconductor switches are turned on and off; a second inverter connected for energization by the DC input voltage, including four additional controllable semiconductor switches connected to regulate both the direction and the level of current flow through the second AC load as different pairs of the semiconductor switches in the second inverter circuit are turned on and off; and a digital control circuit, connected to control the on and off times of the controllable semiconductor switches, including a clock circuit and first and second countdown circuits connected to receive timing pulses frOm the clock circuit, the first countdown circuit being connected to regulate the number of pulses in each half-cycle of the composite AC output voltages, and the second countdown circuit being connected to maintain the composite AC output voltages displaced in phase with respect to each other by a predetermined amount.
Claim 8
Independent Claim
226 words
A system for energizing first and second AC loads from a DC input voltage by providing first and second composite AC output voltages displaced in phase relative to each other, each composite AC output voltage having a plurality of pulses in each half-cycle, which system comprises: a first inverter connected for energization by the DC input voltage, including four controllable semiconductor switches connected to regulate both the direction and the level of current flow through the first AC load as different pairs of the semiconductor switches are turned on and off; a second inverter connected for energization by the DC input voltage, including four additional controllable semiconductor switches connected to regulate both the direction and the level of current flow through the second AC load as different pairs of the semiconductor switches in the second inverter circuit are turned on and off; and a digital control circuit, connected to control the on and off times of the controllable semiconductor switches, including a clock circuit and first and second countdown circuits connected to receive timing pulses frOm the clock circuit, the first countdown circuit being connected to regulate the number of pulses in each half-cycle of the composite AC output voltages, and the second countdown circuit being connected to maintain the composite AC output voltages displaced in phase with respect to each other by a predetermined amount.
Claim 9
Dependent Claim
30 words
An energizing system as claimed in claim 6, in which said first and second AC loads are the windings of a two-phase electrical motor connected to drive a mechanical load.
Claim 10
Dependent Claim
38 words
An energizing system as claimed in claim 6, and further comprising a chopper circuit coupled between a DC input circuit and said first and second inverters, to minimize fluctuations in the DC input voltage supplied to the inverters.
Claim 11
Dependent Claim
124 words
An energizing system as claimed in claim 6, in which said digital control circuit includes a toggle flip-flop circuit coupled to said first countdown circuit and to two of the four controllable semiconductor switches in the first inverter to provide first trigger pulses of a duration approximately a half-cycle of the resultant AC output voltages, and a set-reset flip-flop circuit connected for regulation by said second countdown circuit and by the toggle flip-flop circuit, to provide second trigger pulses to two of the four controllable semiconductor switches in the second inverter, which second trigger pulses are approximately equal in time duration but displaced in phase relative to the first trigger pulses, the extent of the phase displacement being determined by said second countdown circuit.
Claim 12
Dependent Claim
77 words
An energizing system as claimed in claim 9, in which said digital control circuit further includes a bilevel, adjustable delay circuit connected to provide trigger pulses delayed in time relative to said timing pulses for application to those controllable semiconductor switches in the first and second inverters which are not switched by the first or second trigger pulses, and means for adjusting the extent of the time delay between the delayed trigger pulses and the timing pulses.
Claim 13
Independent Claim
385 words
A system for energizing the first and second windings of a multiphase AC motor from a DC input voltage by providing first and second resultant AC output voltages displaced in phase by 90* relative to each other for application to the motor windings, each resultant AC output voltage having four pulses in each half-cycle, which system comprises: a first inverter connected for energization by the DC input voltage, including four controllable semiconductor switches connected to regulate both the direction and the level of current flow through the first motor winding as different pairs of the semiconductor switches are turned on and off; a second inverter connected for energization by the DC input voltage, including four additional controllable semiconductor switches connected to regulate both the direction and the level of current flow through the second motor winding as different pairs of the semiconductor switches in the second inverter circuit are turned on and off; and a digital control circuit, connected to provide trigger pulses which regulate the on and off times of the semiconductor switches, including a clock circuit for providing a series of timing pulses, a divide-by-4 circuit connected to receive the timing pulses, a JK flip-flop coupled to the divide-by-4 circuit and to first and second ones of the four semiconductor switches in the first inverter to provide a first set of trigger pulses of extended duration approximating a half-cycle of the resultant AC output voltages, an RS flip-flop circuit connected to provide a second set of trigger pulses to first and second ones of the semiconductor switches in the second inverter, which second set includes trigger pulses approximately equal in time duration but displaced in phase relative to the trigger pulses in the first set, a divide-by-2 circuit connected to receive the timing pulses and to provide output pulses for establishing and maintainiNg the phase displacement between the first and second sets of trigger pulses, circuit means, including the divide-by-2 circuit and the JK flip-flop, for regulating operation of the RS flip-flop, and a circuit for providing a third set of trigger pulses delayed relative to the timing pulses for application to the third and fourth semiconductor switches in both inverter circuits, including means for adjusting the extent of the time delay between the timing pulses and the third set of trigger pulses.
Claim 14
Independent Claim
385 words
A system for energizing the first and second windings of a multiphase AC motor from a DC input voltage by providing first and second resultant AC output voltages displaced in phase by 90* relative to each other for application to the motor windings, each resultant AC output voltage having four pulses in each half-cycle, which system comprises: a first inverter connected for energization by the DC input voltage, including four controllable semiconductor switches connected to regulate both the direction and the level of current flow through the first motor winding as different pairs of the semiconductor switches are turned on and off; a second inverter connected for energization by the DC input voltage, including four additional controllable semiconductor switches connected to regulate both the direction and the level of current flow through the second motor winding as different pairs of the semiconductor switches in the second inverter circuit are turned on and off; and a digital control circuit, connected to provide trigger pulses which regulate the on and off times of the semiconductor switches, including a clock circuit for providing a series of timing pulses, a divide-by-4 circuit connected to receive the timing pulses, a JK flip-flop coupled to the divide-by-4 circuit and to first and second ones of the four semiconductor switches in the first inverter to provide a first set of trigger pulses of extended duration approximating a half-cycle of the resultant AC output voltages, an RS flip-flop circuit connected to provide a second set of trigger pulses to first and second ones of the semiconductor switches in the second inverter, which second set includes trigger pulses approximately equal in time duration but displaced in phase relative to the trigger pulses in the first set, a divide-by-2 circuit connected to receive the timing pulses and to provide output pulses for establishing and maintainiNg the phase displacement between the first and second sets of trigger pulses, circuit means, including the divide-by-2 circuit and the JK flip-flop, for regulating operation of the RS flip-flop, and a circuit for providing a third set of trigger pulses delayed relative to the timing pulses for application to the third and fourth semiconductor switches in both inverter circuits, including means for adjusting the extent of the time delay between the timing pulses and the third set of trigger pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |