US3603856A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Acceleration-deceleration current limit
Assignee: Louis Allis Co
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Filing: 1969-06-06
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Granted: 1971-09-07
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Expires: 1989-06-06
Abstract
Abstract A current limit for an AC motor drive that is operative whenever motor speed change is commanded and motor current exceeds the current limit value. The rate of change of motor speed is controlled to maintain maximum motor current, i.e., motor current substantially equal to the current limit. This is achieved by moderating the rate of change command to the motor drive circuit in accordance with the amount of motor current in excess of the current limit.
Inventors
- 👤 David R Zalar
- 👤 Eugene L Bilich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:51
CPC Classifications
H; H02; H02P; H02P23/00; H02P23/20; H02P27/00; H02P27/04; H02P27/047
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
In a drive system for an AC motor, said drive system having a power supply means for controlling the speed condition of the motor in direct response to an input signal thereto, accelerating or decelerating changes in said speed condition producing excessive current in the motor, an acceleration-deceleration current limit circuit comprising: speed signal means for providing a signal corresponding to motor speed; means for establishing a current limit magnitude for motor current; means for determining motor current in excess of said current limit magnitude caused by a motor speed change and for developing a current error signal proportional to said excess; and signal rate of change control means coupled to the power supply means of the drive system, said control means being responsive to said speed signal for providing said speed signal to said power supply means as to input signal thereto, said control means being further responsive to said current error signal for limiting the rate of change of said input signal to that necessary to maintain motor current substantially at said current limit magnitude during Speed change.
Claim 2
Dependent Claim
180 words
In a drive system for an AC motor, said drive system having a power supply means for controlling the speed condition of the motor in direct response to an input signal thereto, accelerating or decelerating changes in said speed condition producing excessive current in the motor, an acceleration-deceleration current limit circuit comprising: speed signal means for providing a signal corresponding to motor speed; means for establishing a current limit magnitude for motor current; means for determining motor current in excess of said current limit magnitude caused by a motor speed change and for developing a current error signal proportional to said excess; and signal rate of change control means coupled to the power supply means of the drive system, said control means being responsive to said speed signal for providing said speed signal to said power supply means as to input signal thereto, said control means being further responsive to said current error signal for limiting the rate of change of said input signal to that necessary to maintain motor current substantially at said current limit magnitude during Speed change.
Claim 3
Dependent Claim
76 words
An acceleration-deceleration current limit circuit as recited in claim 1 wherein said signal rate of change control means is defined as responsive to said speed signal for developing a predetermined rate of change in said input signal in the absence of a current error signal and is further defined as responsive to the presence of said current error signal for moderating said predetermined rate of change in accordance with the magnitude of said current error signal.
Claim 4
Dependent Claim
83 words
An acceleration-deceleration current limit circuit as recited in claim 2 including timing means coupled to the output of said signal rate of change control means and responsive to said speed signal for producing timing pulses indicative of the duration and direction of changes in said speed signal, said circuit further including gate means responsive to said timing pulses for causing said current error signal to be applied to said signal rate of change control means only during the presence of said timing pulses.
Claim 5
Dependent Claim
39 words
An acceleration-deceleration current limit circuit as recited in claim 1 wherein said signal rate of change control means includes a capacitor-charging circuit having a variable signal rate of change output up to a maximum signal rate of change output.
Claim 6
Dependent Claim
67 words
An acceleration-deceleration current limit circuit as recited in claim 1 wherein said power supply means energizes the motor with constant volts per cycle energization over the speed range of the motor, said signal rate of change control means providing the speed signal to said power supply means for controlling the volts per cycle energization applied to the motor, and the speed thereof, proportional to said speed signal.
Claim 7
Dependent Claim
76 words
An acceleration-deceleration current limit circuit as recited in claim 5 wherein said power supply includes an inverter, controlled rectifier means to supply an adjustable voltage to said inverter and an oscillator for controlling the frequency of the AC voltage output of said inverter, said signal rate of change control means providing the speed signal to said inverter and controlled rectifier means for applying constant volts per cycle energization to the motor over the speed range thereof.
Claim 8
Dependent Claim
121 words
An acceleration-deceleration current limit circuit as recited in claim 3 wherein said timing means includes means responsive to the direction of signal change in said speed signal for producing a timing pulse of one polarity responsive to an accelerating speed signal change and a pulse of the other polarity responsive to a decelerating speed signal change, and said gate means includes a first gate circuit responsive to a timing pulse of one polarity to apply said current error signal to said signal rate of change control means under acceleration conditions and a second gate circuit responsive to a timing pulse of the other polarity to apply said current error signal to said signal rate of change control means under deceleration conditions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |