US3603746A
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US
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Measurement of average duty cycle
Assignee: AT&T Inc
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Filing: 1969-11-24
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Granted: 1971-09-07
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Expires: 1989-11-24
Abstract
Abstract Digital technique is used to control four clock pulse counters for measuring an approximation of the average percent break or the pulsing speed over a series of telephone dial pulse periods. For percent break, up-counter B serially counts pips of frequency 100f during the sum of nine break intervals, the total B count is placed as the same count in reentrant down-counter A and counter B is cleared. Counter D accumulates pips of frequency f during the entire time of nine pulse periods. Dividing circuitry causes down-counting in counter A and up-counting in counter C under the control of a high-speed clock. Counter C is recycled each time it accumulates a count equal to the count in counter D. Downcounting in A and up-counting in C are stopped when A down-counts from zero to capacity count. The number of recyclings of counter C is registered in the cleared counter B as a percent. Fractional control circuitry takes into account any remainder in counter C. Visual display is provided of the answer in percent. For pulsing speed, a prescribed count is placed in down-counter A and the accumulated count in counter D corresponding to the nine pulse periods is used as in percent break to provide an answer approximating the pulsing speed.
Inventors
- 👤 Robert B Heick
- 👤 Henry Mann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:07
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/04; H; H04; H04M; H04M1/00; H04M1/24
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
257 words
Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first pulse count register; B. a second pulse count register; C. a first source of pulses recurring at a constant frequency substantially greater then the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; E. a second source of pulses recurring at a constant frequency an integral multiple of ten times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals for causing the first register to register a pulse count of the number of pulses from the second source occurring during the sum of all time intervals between the signals of the alternate pairs; G. means controlled by the last signal of the series for causing the pulse count in the second register to be repeatedly and dissipatively subtracted from the pulse count in the first register so as to dissipatively reduce the pulse count in the first register; H. and, means controlled by the subtracting means for indicating the number of subtractions required to cause the pulse count in the first register to be completely dissipated.
Claim 2
Dependent Claim
257 words
Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first pulse count register; B. a second pulse count register; C. a first source of pulses recurring at a constant frequency substantially greater then the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; E. a second source of pulses recurring at a constant frequency an integral multiple of ten times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals for causing the first register to register a pulse count of the number of pulses from the second source occurring during the sum of all time intervals between the signals of the alternate pairs; G. means controlled by the last signal of the series for causing the pulse count in the second register to be repeatedly and dissipatively subtracted from the pulse count in the first register so as to dissipatively reduce the pulse count in the first register; H. and, means controlled by the subtracting means for indicating the number of subtractions required to cause the pulse count in the first register to be completely dissipated.
Claim 3
Dependent Claim
232 words
Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first pulse count register; B. a second pulse count register; C. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last sIgnals; E. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals for causing the first register to register a pulse count of the number of pulses from the second source occurring during the sum of all time intervals between the signals of the alternate pairs; G. means controlled by the last signal of the series for causing the pulse count in the second register to be repeatedly and dissipatively subtracted from the pulse count in the first register so at to dissipatively reduce the pulse count in the first register, subtracting means comprising
Claim 4
Dependent Claim
232 words
Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first pulse count register; B. a second pulse count register; C. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last sIgnals; E. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals for causing the first register to register a pulse count of the number of pulses from the second source occurring during the sum of all time intervals between the signals of the alternate pairs; G. means controlled by the last signal of the series for causing the pulse count in the second register to be repeatedly and dissipatively subtracted from the pulse count in the first register so at to dissipatively reduce the pulse count in the first register, subtracting means comprising
Claim 5
Dependent Claim
4 words
a resettable dividing counter,
Claim 6
Dependent Claim
4 words
a resettable dividing counter,
Claim 7
Dependent Claim
87 words
and a count comparator interconnected to the dividing counter and to the register and to the reset terminal for energizing the reset terminal whenever the count in the dividing counter equals the count in the register; B. and, the means for causing the reset up counter to contain a registration indicative of the number of times the dividing counter is reset comprises interconnection of the reset terminal with the up counter so that the reset up counter counts the number of times the reset terminal is energized.
Claim 8
Dependent Claim
87 words
and a count comparator interconnected to the dividing counter and to the register and to the reset terminal for energizing the reset terminal whenever the count in the dividing counter equals the count in the register; B. and, the means for causing the reset up counter to contain a registration indicative of the number of times the dividing counter is reset comprises interconnection of the reset terminal with the up counter so that the reset up counter counts the number of times the reset terminal is energized.
Claim 9
Dependent Claim
28 words
and means controlled by the dividing means for causing the reset up counter to contain a registration indicative of the number of times the dividing counter is reset.
Claim 10
Dependent Claim
28 words
and means controlled by the dividing means for causing the reset up counter to contain a registration indicative of the number of times the dividing counter is reset.
Claim 11
Dependent Claim
4 words
a resettable dividing counter,
Claim 12
Dependent Claim
4 words
a resettable dividing counter,
Claim 13
Dependent Claim
73 words
for transferring the pulse count from the up counter to the down counter; H. means controlled by the last signal of the series for causing the pulse count in the register to be repeatedly and dissipatively subtracted from the pulse count in the down counter I. and, means controlled by the subtracting means for indicating the number of subtractions required to cause the pulse count in the down counter to be completely dissipated.
Claim 14
Dependent Claim
73 words
for transferring the pulse count from the up counter to the down counter; H. means controlled by the last signal of the series for causing the pulse count in the register to be repeatedly and dissipatively subtracted from the pulse count in the down counter I. and, means controlled by the subtracting means for indicating the number of subtractions required to cause the pulse count in the down counter to be completely dissipated.
Claim 15
Dependent Claim
40 words
means controlled by the last signal of the series a. for causing the dividing counter to count control pulses b. and for causing each counted control pulse to subtract one pulse count from the pulse count in the first register,
Claim 16
Dependent Claim
40 words
means controlled by the last signal of the series a. for causing the dividing counter to count control pulses b. and for causing each counted control pulse to subtract one pulse count from the pulse count in the first register,
Claim 17
Dependent Claim
50 words
means controlled by the last signal of the series a. for resetting the up counter to zero count b. and for causing the dividing counter to count control pulses c. and for causing each counted control pulse to subtract one pulse count from the pulse count in the down counter,
Claim 18
Dependent Claim
50 words
means controlled by the last signal of the series a. for resetting the up counter to zero count b. and for causing the dividing counter to count control pulses c. and for causing each counted control pulse to subtract one pulse count from the pulse count in the down counter,
Claim 19
Dependent Claim
87 words
The invention defined in claim 2 wherein: A. the first register comprises a down counter controllable to change its registration from zero count to maximum count upon the subtraction of one pulse count from zero count; B. and, the means for causing control pulse counting in the dividing counter and control pulse subtracting in the down counter comprises means controlled by the down counter for allowing the counting and subtracting of control pulses until the count in the down counter changes from zero count to maximum count.
Claim 20
Dependent Claim
77 words
The invention defined in claim 3 wherein the allowing means comprises: A. gating means interconnecting the source of control pulses with the dividing counter and with the down counter; B. and, means controlled by the down counter for controlling the gating means so that control pulses are allowed to pass through the gating means to the dividing counter and to the down counter until the count in the down counter changes from zero count to maximum count.
Claim 21
Dependent Claim
57 words
and means controlled jointly by the dividing counter and by the second register for causing the dividing counter to be reset to zero count whenever the count in the dividing counter equals the count in the second register; H. and, means controlled by the subtracting means for indicating the number of times the dividing counter is reset.
Claim 22
Dependent Claim
57 words
and means controlled jointly by the dividing counter and by the second register for causing the dividing counter to be reset to zero count whenever the count in the dividing counter equals the count in the second register; H. and, means controlled by the subtracting means for indicating the number of times the dividing counter is reset.
Claim 23
Dependent Claim
42 words
and means controlled jointly by the dividing counter and by the register for causing the dividing counter to be reset to zero count whenever the count in the dividing counter equals the count in the register; B. and, the indicating means comprises
Claim 24
Dependent Claim
42 words
and means controlled jointly by the dividing counter and by the register for causing the dividing counter to be reset to zero count whenever the count in the dividing counter equals the count in the register; B. and, the indicating means comprises
Claim 25
Dependent Claim
73 words
The invention defined in claim 4 wherein the means for controlling the gating means comprises: A. means controlled by the down counter for providing a stop signal when the count in the down counter changes from zero count to maximum count; B. and means for applying the stop signal to the gating means to stop further control pulses from passing through the gating means to the dividing counter and to the down counter.
Claim 26
Dependent Claim
152 words
Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a pulse up counter; B. a pulse down counter; C. a pulse count register; D. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; E. means controlled by the first and last signals of the series for causing the register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; F. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; G. means controlled by alternate consecutive pairs of signals
Claim 27
Dependent Claim
152 words
Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a pulse up counter; B. a pulse down counter; C. a pulse count register; D. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; E. means controlled by the first and last signals of the series for causing the register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; F. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; G. means controlled by alternate consecutive pairs of signals
Claim 28
Dependent Claim
18 words
The invention defined in claim 6 wherein: A. the up counter is resettable; B. the subtracting means comprises
Claim 29
Dependent Claim
83 words
The invention defined in claim 7 wherein: A. the down counter is controllable to change its registration from zero count to maximum count upon the subtraction of one pulse count from zero count; B. and, the means for causing control pulse counting in the dividing counter and control pulse subtracting in the down counter comprises means controlled by the down counter for allowing the counting and subtracting of control pulses until the count in the downcounter changes from zero count to maximum count.
Claim 30
Dependent Claim
76 words
The invention defined in claim 8 wherein the allowing means comprises; A. gating means interconnecting the source of control pulses with the dividing counter and with the downcounter; B. and, means controlled by the down counter for controlling the gating means so that control pulses are allowed to pass through the gating means to the dividing counter and to the down counter until the count in the down counter changes from zero count to maximum count.
Claim 31
Dependent Claim
73 words
The invention defined in claim 9 wherein the means for controlling the gating means comprises A. means controlled by the down counter for providing a stop signal when the count in the down counter changes from zero count to maximum count B. and means for applying the stop signal to the gating means to stop further control pulses from passing through the gating means to the dividing counter and to the down counter.
Claim 32
Dependent Claim
22 words
The invention defined in claim 10 wherein: A. the means for causing the dividing counter to be reset to zero count comprises
Claim 33
Dependent Claim
52 words
The invention defined in claim 10 further comprising logic circuitry A. connected to the dividing counter B. and controlled the by stop signal to derive from any count then remaining in the dividing counter a fraction signal representative of the approximate fraction the remaining count is of the count in the registEr.
Claim 34
Dependent Claim
35 words
The invention defined in claim 12 wherein the indicating means further comprises means controlled by the fraction signal for causing the reset up counter to also contain a registration indicative of the approximate fractional count.
References Cited (Backward Citations)
US3243526A
Cited
US3410967A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |