Measurement of average duty cycle

Claim 2

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first register; B. a second register; C. means controlled by alternate consecutive pairs of signals for causing the first register to contain a registration indicative of the sum of all time intervals between the signals of the alternate pairs; D. means controlled by the first and last signals of the series for causing the second register to contain a registration indicative of the sum of all time periods between the first and last signals; E. and, means controlled by the last signal of the series for dividing the registration in the first register By the registration in the second register.

Claim 3

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first register; B. a second register; C. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; E. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals for causing the first register to register a pulse count of the number of pulses from the second source occurring during the sum of all time intervals between the signals of the alternate pairs; G. and, means controlled by the last signal of the series for dividing the pulse count in the first register by the pulse count in the second register.

Claim 4

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first register; B. a second register; C. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; E. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals for causing the first register to register a pulse count of the number of pulses from the second source occurring during the sum of all time intervals between the signals of the alternate pairs; G. and, means controlled by the last signal of the series for dividing the pulse count in the first register by the pulse count in the second register.

Claim 5

means controlled by the last signal of the series for applying shift pulses to the shift register,

Claim 6

means controlled by the last signal of the series for applying shift pulses to the shift register,

Claim 7

and means controlled by the primary counter for transferring to the secondary counter the nine''s complement of the count in the primary counter.

Claim 8

and means controlled by the primary counter for transferring to the secondary counter the nine''s complement of the count in the primary counter.

Claim 9

and a secondary binary counter haviNg a plurality of binary counting stages equal in number to the plurality of stages in the primary counter; B. and, the setting means comprises

Claim 10

and a secondary binary counter haviNg a plurality of binary counting stages equal in number to the plurality of stages in the primary counter; B. and, the setting means comprises

Claim 11

means controlled by the last signal of the series for applying control pulses to the shifT register to cause each stored pulse to shift to the next succeeding element in response to each shift control pulse,

Claim 12

means controlled by the last signal of the series for applying control pulses to the shifT register to cause each stored pulse to shift to the next succeeding element in response to each shift control pulse,

Claim 13

and for causing each priorly stored pulse to be shifted to the element next succeeding the element priorly storing the pulse; C. the adding means comprises

Claim 14

and for causing each priorly stored pulse to be shifted to the element next succeeding the element priorly storing the pulse; C. the adding means comprises

Claim 15

and for causing the secondary register to register therein the complement of the pulse count in the primary register; G. means controlled by the last signal of the series for causing the pulse count in the second register to be repeatedly and cumulatively added to the pulse count in the secondary register; H. and, means controlled by the adding means for indicating the number of additions required to cause the cumulative pulse count in the secondary register to exceed the capacity of the secondary register.

Claim 16

and for causing the secondary register to register therein the complement of the pulse count in the primary register; G. means controlled by the last signal of the series for causing the pulse count in the second register to be repeatedly and cumulatively added to the pulse count in the secondary register; H. and, means controlled by the adding means for indicating the number of additions required to cause the cumulative pulse count in the secondary register to exceed the capacity of the secondary register.

Claim 17

and a secondary pulse count register of the same given count capacity; B. a second register; C. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; E. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals

Claim 18

and a secondary pulse count register of the same given count capacity; B. a second register; C. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of a pair; D. means controlled by the first and last signals of the series for causing the second register to register a pulse count of the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; E. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; F. means controlled by alternate consecutive pairs of signals

Claim 19

means for causing the first element to next succeed the last element so that the stored pulses recirculate through the shift register as long as shift control pulses are applied thereto,

Claim 20

means for causing the first element to next succeed the last element so that the stored pulses recirculate through the shift register as long as shift control pulses are applied thereto,

Claim 21

means for causing pulses shifted from the last storage element to be stored in the first storage element,

Claim 22

means for causing pulses shifted from the last storage element to be stored in the first storage element,

Claim 23

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first register comprising

Claim 24

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first register comprising

Claim 25

and means for causing pulses shifted from the last storage element to be added to the pulse count in the secondary counter; B. and, the preventing means prevents further application of shift pulses to the shift register when the secondary counter is set from capacity count to zero count.

Claim 26

and means for causing pulses shifted from the last storage element to be added to the pulse count in the secondary counter; B. and, the preventing means prevents further application of shift pulses to the shift register when the secondary counter is set from capacity count to zero count.

Claim 27

The invention defined in claim 3 wherein: A. the second register comprises a serial pulse shift register having a plurality from first to last of pulse storage elements greater in number than the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; B. the means for causing the second register to register a pulse count comprises means controlled by each pulse from the first source

Claim 28

and means for causing each stored pulse shifted from the last element to the first element to be added to the pulse count in the secondary register; D. and, the indicating means indicates the number of recirculations required to cause the cumulative pulse count in the secondary register to exceed the capacity thereof.

Claim 29

and means for causing each stored pulse shifted from the last element to the first element to be added to the pulse count in the secondary register; D. and, the indicating means indicates the number of recirculations required to cause the cumulative pulse count in the secondary register to exceed the capacity thereof.

Claim 30

The invention defined in claim 4 wherein the indicating means comprises A. means controlled by the secondary register for preventing further application of control pulses to the shift register when the cumulative pulse count in the secondary register exceeds the capacity thereof B. and means controlled by the adding means for counting the number of recirculations occurring during the application of control pulses to the shift register.

Claim 31

The invention defined in claim 5 further comprising means controlled by the preventing means when the cumulative pulse count in the secondary register exceeds the capacity thereof A. for detecting the number of pulses remaining in the shift register B. and for controlling the indicating means to indicate a fractional recirculation count represented by that remaining number of pulses.

Claim 32

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of any pair in the series; B. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; C. binary pulse counting means having a count capacity greater than the number of pulses from the second source occurring during the sum of all time intervals between the signals of alternate consecutive pairs of signals in the series; D. a pulse shift register having a plurality of serially related storage elements greater in number than the number of pulses from the first source occurring during the sum of all time periods between the first and last signals in the series; E. setting means controlled by alternate consecutive pairs of signals for causing the binary counting means to be set to a count equal to the nine''s complement of the number of pulses from the second source occurring during the sum of all time intervals between the signals of alternate pairs; F. storing means controlled by the first and last signals of the series for causing the shift register to store in consecutive storage elements the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; G. adding means controlled by the last signal of the series for causing the pulses stored in the shift register to repeatedly circulate through the shift register while being cumulatively added to the pulse count in the binary counting means; H. means controlled by the binary counting means for preventing further circulation and adding when the cumulative pulse count in the binary counting means exceeds the capacity thereof; I. and, means controlled by the adding means for indicating the number of circulations required to cause the cumulative pulse count in the binary counting means to exceed the capacity thereof.

Claim 33

Circuitry for measuring the average time interval between alternate consecutive pairs of signals among an odd series of such signals in terms of a percentage of the average time period between consecutive odd signals comprising: A. a first source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of consecutive signals of any pair in the series; B. a second source of pulses recurring at a constant frequency an integral multiple of 10 times the recurrence frequency of pulses from the first source; C. binary pulse counting means having a count capacity greater than the number of pulses from the second source occurring during the sum of all time intervals between the signals of alternate consecutive pairs of signals in the series; D. a pulse shift register having a plurality of serially related storage elements greater in number than the number of pulses from the first source occurring during the sum of all time periods between the first and last signals in the series; E. setting means controlled by alternate consecutive pairs of signals for causing the binary counting means to be set to a count equal to the nine''s complement of the number of pulses from the second source occurring during the sum of all time intervals between the signals of alternate pairs; F. storing means controlled by the first and last signals of the series for causing the shift register to store in consecutive storage elements the number of pulses from the first source occurring during the sum of all time periods between the first and last signals; G. adding means controlled by the last signal of the series for causing the pulses stored in the shift register to repeatedly circulate through the shift register while being cumulatively added to the pulse count in the binary counting means; H. means controlled by the binary counting means for preventing further circulation and adding when the cumulative pulse count in the binary counting means exceeds the capacity thereof; I. and, means controlled by the adding means for indicating the number of circulations required to cause the cumulative pulse count in the binary counting means to exceed the capacity thereof.

Claim 34

The invention defined in claim 7 wherein: A. the binary counting means comprises

Claim 35

The invention defined in claim 8 wherein: A. the secondary counter is settable from capacity count to zero count upon the addition of a pulse; B. and, the preventing means is controlled by the secondary counter for preventing further circulation and adding when the secondary counter is set from capacity count to zero count.

Claim 36

The invention defined in claim 9 wherein: A. the adding means comprises

Claim 37

The invention defined in claim 10 wherein the indicating means is controlled by pulses shifted from the last storage element for counting the number of times the pulse count in the shift register is circulated.

Claim 38

The invention defined in claim 11 wherein: A. the means for causing pulses from the second source to be counted in the primary counter comprises a transmitting gate connected between the second source and the primary counter and controlled by alternate consecutive pairs of signals for allowing pulses to be transmitted from the second source to the primary register only during the time intervals between signals of the pairs; B. and, the means for transferring to the secondary counter the nine''s complement of the count in the primary register comprises a plurality of transfer gates connected between corresponding stages of the primary and secondary counters.

Claim 39

The invention defined in claim 12 wherein: A. the means for applying shift pulses to the shift register comprises a shift gate connected between the source of shift pulses and the shift register and controlled by the last signal of the series for allowing shift pulses to be transmitted from the source of shift pulses to the shift register; B. and, the preventing means causes the shift gate to prevent further transmission of shift pulses to the shift register when the secondary counter is set from capacity count to zero count.

Claim 40

The invention defined in claim 11 further comprising means controlled by the preventing means when the secondary counter is set from capacity count to zero count A. for detecting the number of pulses remaining in the shift register B. and for controlling the indicating means to indicate a fractional circulation count represented by that remaining number of pulses.

Claim 41

The invention defined in claim 11 wherein: A. the means for transferring to the secondary counter the nine''s complement of the count in the primary counter is controlled by the last signal of the series to transfer the then cumulative count in the primary counter and to clear the primary counter to zero count; B. and, the indicating means comprises the cleared primary counter.

Claim 42

The invention defined in claim 15 further comprising means controlled by the preventing means when the secondary counter is set from capacity count to zero count A. for counting the number of pulses remaining in the shift register B. and for controlling the primary counter to indicate that remaininG pulse count as a fractional circulation count.