US3602743A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for producing an output pulse of predetermined width after a predetermined delay
Assignee: Phillips Petroleum Co
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Filing: 1969-04-09
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Granted: 1971-08-31
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Expires: 1989-04-09
Abstract
Abstract A pulse delay circuit has two gate circuits cooperating with two resistance-capacitance units, one of which controls the delay interval and the other of which controls the width of the output pulse.
Inventors
- 👤 Earl L De Shazo Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:42
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/01; H03K5/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
208 words
A pulse delay circuit comprising, in combination, a first set and a second set of first and second parallel connecTed transistors; an output transistor; each of said transistors having a base, a collector, and an emitter; a first condenser connecting the collectors of said first set of transistors to the base of the first one of said second set of transistors, a first resistance arranged to discharge said condenser; a second condenser connecting the collectors of said second set of two transistors to the base of said output transistor; a second resistance arranged to discharge said second condenser; means for applying an input pulse to the base of the first one of said first set of two transistors; means for feeding back the output of said second set to the base of the second transistor of said first set; means for feeding back the output signal from the collector of said output transistor to the base of the second transistor of said second set; means for connecting the emitters of said first set of transistors to a reference voltage; means for connecting the emitters of said second set of transistors to a reference voltage; and means for connecting the emitter of said output transistor to a reference voltage.
Claim 2
Dependent Claim
208 words
A pulse delay circuit comprising, in combination, a first set and a second set of first and second parallel connecTed transistors; an output transistor; each of said transistors having a base, a collector, and an emitter; a first condenser connecting the collectors of said first set of transistors to the base of the first one of said second set of transistors, a first resistance arranged to discharge said condenser; a second condenser connecting the collectors of said second set of two transistors to the base of said output transistor; a second resistance arranged to discharge said second condenser; means for applying an input pulse to the base of the first one of said first set of two transistors; means for feeding back the output of said second set to the base of the second transistor of said first set; means for feeding back the output signal from the collector of said output transistor to the base of the second transistor of said second set; means for connecting the emitters of said first set of transistors to a reference voltage; means for connecting the emitters of said second set of transistors to a reference voltage; and means for connecting the emitter of said output transistor to a reference voltage.
Claim 3
Dependent Claim
32 words
The circuit of claim 1 wherein the time constant of said first condenser and said first resistance is substantially greater than the time constant of said second condenser and said second resistance.
Claim 4
Dependent Claim
64 words
The circuit of claim 1 further comprising a sixth transistor having its base connected to said first condenser, its emitter connected to the base of the first transistor in said second set of transistors and its collector connected to the collectors of said second set of transistors, said sixth transistor being connected in the Darlington configuration with the first transistor of said second set.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |