Circuit for generating a pulse in response to a radiation burst

Claim 2

A solid state pulse generator circuit capable of selfactivating or external activating in response to a radiation burst and continuing to operate during said bust with a pulse output substantially constant regardless of environment comprising a resistance-capacitance timing circuit, transistor means for generating an output pulse, said generating means having a control element thereof connected to said timing circuit and activated by a current therein, transistor triggering means for initiating a current in said timing circuit in response to said radiation burst to activate said generating means, means for sustaining said current of said triggering means for the desired duration of said output pulse, said sustaining means being regeneratively coupled to said triggering means by said timing circuit and resistive means in each current discharge path of said circuit for limiting flow of current through each of said circuit elements.

Claim 3

The generator of claim 1 further comprising means for discharging the capacitor of said timing circuit after termination of the output pulse.

Claim 4

The generator of claim 1 further comprising a filter circuit connected to an input voltage source including a ceramic capacitor connected between said voltage source and ground to prevent instantaneous variations of said voltage source from affecting the operation of said generator, said capacitor being resistant to said radiation burst.

Claim 5

The generator of claim 1 further comprising a potential sensing circuit connected between said triggering means and a ground potential, said sensing circuit being operable to assure that said triggering means ceases conduction at the termination of the desired output pulse duration.

Claim 6

The generator of claim 1 wherein said sustaining means includes a transistor regeneratively coupled to said timing circuit and triggering means and further comprising a capacitance swamping circuit connected between the emitter and the base of said transistor of said sustaining means.

Claim 7

The generator of claim 1 wherein the transistor of said generating means is connected as an emitter follower with its base connected to said timing circuit.

Claim 8

The generator of claim 1 wherein the collector of said transistor of said sustaining means and the base of said transistor of said triggering means are interconnected by said timing circuit.

Claim 9

The pulse generator of claim 8 wherein said generating means comprises a first NPN transistor having an emitter, base, and collector, said output pulse being derived at the emitter of said first NPN transistor; said sustaining means comprises a PNP transistor having an emitter, base, and collector, the emitter of said PNP transistor being connected to the collector of said first NPN transistor, and the collector of said PNP transistor being connected to the base of said first NPN transistor; said triggering means comprises a second NPN transistor having an emitter, base and collector; and said timing circuit comprises a first resistor, a capacitor, and a diode connected in series between the collector of said PNP transistor and the base of said second NPN transistor; and further comprising a second resistor connecting the emitter of said first NPN transistor to a ground potential; a third resistor interconnecting the base to the emitter of said first NPN transistor; a fourth resistor interconnecting the base and the emitter of said PNP transistor; a fifth resistor connecting the emitter of said second NPN transistor to a ground potential; a sixth resistor interconnecting the base of said PNP transistor and the collector of said second NPN transistor; two discharge resistors, each connecting one side of said capacitor of said timing circuit to a ground potential; and a potential sensing circuit comprising a diode and a seventh resistor connected in series, and connecting the base of said second NPN transistor to a ground potential, whereby when an input voltage is applied to said emitter of said PNP transistor and biasing voltages are applied to the emitter, of said second NPN transistor, and an input pulse is applied between the capacitor and first resistor of said timing circuit and any other point of the circuit, a voltage pulse of duration proportional to the time constant of said resistor and said capacitor in said timing circuit is produced at the emitter of said first NPN transistor.