US3602707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analogue multiplier-divider circuit including a pair of cross-coupled transistor circuits
Assignee: Individual
•
Filing: 1969-05-23
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Granted: 1971-08-31
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Expires: 1989-05-23
Abstract
Abstract A circuit capable of performing analogue multiplication or division is shown. The analogue multiplier/divider circuit has balancing amplifiers respectively connected with transistor circuits, where the transistor circuits provide the nonlinear function necessary for analogue multiplier or divider functions.
Inventors
- 👤 Howard E Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:30
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
421 words
Analog multiplier/divider circuitry for alternatively multiplying or dividing a pair of quantities represented by timevarying current input signals comprising: first, second, third and fourth transistors, each having base, emitter, and collector electrodes; first, second, third, and fourth balancing amplifier means, each having an output terminal and first and second control terminals; first, second, third, and fourth load means, each having first and second contacts, each of said first contacts coupled in common for coupling to a first source of potential; first, second, third, and fourth input terminals for receiving time-varying current input signals; first coupling means for coupling said first input terminal to said first control terminal of said first amplifier means and said collector electrode of said first transistor; second coupling means for coupling said second input terminal to said first control terminal of said second amplifier means and said collector electrode of said second transistor; third coupling means for coupling said third input terminal to said first control terminal of said third amplifier means and said collector electrode of said third transistor; fourth coupling means for coupling said fourth input terminal to said first control terminal of said fourth amplifier means and said collector electrode of said fourth transistor; fifth coupling means for coupling said emitter electrodes of said first and second transistors in common to said second balancing amplifier means output terminal, said fifth coupling means including means for coupling to a second source of potential; sixth coupling means for coupling said emitter electrodes of said third and fourth transistors in common to said third balancing amplifier means output terminal, said sixth coupling means including means for coupling to said second source of potential; seventh coupling means for coupling said first balancing amplifier output terminal in common to said base electrodes of said first and third transistors; first impedance means for coupling said seventh coupling means to a third source of potential; eighth coupling means for coupling said base electrodes of said second and fourth transistors in common to said third source of potential; second impedance means for coupling said eighth coupling means to said second source of potential; ninth coupling means for coupling said second control terminals of said first, second, third, and fourth balancing amplifier means in common for coupling to said third source of potential; output impedance means coupled intermediate said fourth input terminal and said fourth balancing amplifier means output terminal; and output terminal means coupled to said fourth balancing amplifier means output terminal for alternatively providing the result of analog multiplication or division.
Claim 2
Dependent Claim
421 words
Analog multiplier/divider circuitry for alternatively multiplying or dividing a pair of quantities represented by timevarying current input signals comprising: first, second, third and fourth transistors, each having base, emitter, and collector electrodes; first, second, third, and fourth balancing amplifier means, each having an output terminal and first and second control terminals; first, second, third, and fourth load means, each having first and second contacts, each of said first contacts coupled in common for coupling to a first source of potential; first, second, third, and fourth input terminals for receiving time-varying current input signals; first coupling means for coupling said first input terminal to said first control terminal of said first amplifier means and said collector electrode of said first transistor; second coupling means for coupling said second input terminal to said first control terminal of said second amplifier means and said collector electrode of said second transistor; third coupling means for coupling said third input terminal to said first control terminal of said third amplifier means and said collector electrode of said third transistor; fourth coupling means for coupling said fourth input terminal to said first control terminal of said fourth amplifier means and said collector electrode of said fourth transistor; fifth coupling means for coupling said emitter electrodes of said first and second transistors in common to said second balancing amplifier means output terminal, said fifth coupling means including means for coupling to a second source of potential; sixth coupling means for coupling said emitter electrodes of said third and fourth transistors in common to said third balancing amplifier means output terminal, said sixth coupling means including means for coupling to said second source of potential; seventh coupling means for coupling said first balancing amplifier output terminal in common to said base electrodes of said first and third transistors; first impedance means for coupling said seventh coupling means to a third source of potential; eighth coupling means for coupling said base electrodes of said second and fourth transistors in common to said third source of potential; second impedance means for coupling said eighth coupling means to said second source of potential; ninth coupling means for coupling said second control terminals of said first, second, third, and fourth balancing amplifier means in common for coupling to said third source of potential; output impedance means coupled intermediate said fourth input terminal and said fourth balancing amplifier means output terminal; and output terminal means coupled to said fourth balancing amplifier means output terminal for alternatively providing the result of analog multiplication or division.
Claim 3
Dependent Claim
27 words
Circuitry as in claim 1 wherein said first and third transistors and said second and fourth transistors are matched pairs for providing matched responses to temperature changes.
Claim 4
Dependent Claim
68 words
Circuitry as in claim 1 and further including multiplier input means coupled to predetermined ones of said input terminals for providing time-varying current signals thereto, said multiplier input means including first and second analog voltage input terminals for receiving first and second analog voltage signals, respectively, said first and second analog voltages to be multiplied, and means for converting analog voltage signals so received to time-varying current signals.
Claim 5
Dependent Claim
83 words
Circuitry as in claim 1 and further including four-quadrant analog multiplier input means having first and second analog voltage input terminals for receiving first and second analog voltage signals, respectively, first impedance coupling means for coupling said first analog voltage input terminal to said second and fourth input terminals for providing first time-varying current signals thereto; and second impedance coupling means for coupling said second analog voltage input terminal to said third and fourth input terminals for providing second time-varying current signals thereto.
Claim 6
Dependent Claim
71 words
Circuitry as in claim 1 and further including analog divider input means coupled to predetermined ones of said input terminals for providing time-varying current signals thereto, said analog divider input means including first and second analog voltage input termiNals for receiving first and second analog voltage signals, respectively, said first and second analog voltage signals to be divided; and means for converting analog voltage signals so received to time-varying current signals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |