US3602698A
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Pulse count conversion device using decimal adder-subtracter
Assignee: General Electric Co
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Filing: 1968-06-17
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Granted: 1971-08-31
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Expires: 1988-06-17
Abstract
Abstract A conversion device for converting a train of electric signal pulses indicative of a given quantity, such as position, into a count of standard units of measure. The conversion device comprises a digitally operable, reversible counter and register having digitally operable adder-subtracter circuit means for adding positive or negative increments of count to the register for each input electric signal pulse as determined by the sign of the input electric signal pulses. The overflow from the register is applied to a reversible counter. Each increment of count is proportional to a standard conversion factor for converting the input train of pulses into a count of standard measurement units such as inches or centimeters. The reversible counter preferably comprises a digital decimal counter. The stages of the register are preferably comprised by binary arithmetic stages and the most significant binary stage supplied its overflow count to the least significant decimal stage of the counter as a standard decimal incremental input. The train of input pulses indicative of a quantity to be measured may comprise the output signal pulses of an interferometer position measuring device, and the standard conversion factor added to or subtracted from the reversible counter for each incremental input pulse may be a value representative of the spacing in microinches or micrometers between the fringe count pulses produced by the interferometer position measuring device.
Inventors
- 👤 Hervey E Vigour
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/4912; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/19; G05B19/21; G06F2207/00; G06F2207/491; G06F2207/49125
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
208 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binarycoded decimal number reversible counter for storing decimal numbers in decimal number stages thereof, a binary-coded number register, a binary number adder-subtracter, a source of binary signals in parallel from representing the multidigits of a conversion factor number, the most significant binary signal of said source of binary signals being dimensioned to be one-half of the value of the least significant decimal number stage of said reversible counter, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said binary signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said binary signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal number stage of said counter as a decimal unit incremental input, Said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure.
Claim 2
Dependent Claim
208 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binarycoded decimal number reversible counter for storing decimal numbers in decimal number stages thereof, a binary-coded number register, a binary number adder-subtracter, a source of binary signals in parallel from representing the multidigits of a conversion factor number, the most significant binary signal of said source of binary signals being dimensioned to be one-half of the value of the least significant decimal number stage of said reversible counter, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said binary signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said binary signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal number stage of said counter as a decimal unit incremental input, Said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure.
Claim 3
Dependent Claim
31 words
An arrangement according to claim 1, further comprising means responsive to environmental factors affecting said interferometer for adjusting the value of at least some of said digits of said binary signals.
Claim 4
Dependent Claim
210 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary-coded decimal number reversible counter for storing decimal digits in decimal number stages thereof, a given nondecimal coded number register, an adder-subtracter, a source of given nondecimal coded signals in parallel form representing the multidigits of a conversion factor number, the most significant given nondecimal signal of said source of signals being dimensioned to be one-half of the value of the least significant decimal number stage of said reversible counter, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said decimal signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said decimal signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal digit stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure.
Claim 5
Dependent Claim
210 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary-coded decimal number reversible counter for storing decimal digits in decimal number stages thereof, a given nondecimal coded number register, an adder-subtracter, a source of given nondecimal coded signals in parallel form representing the multidigits of a conversion factor number, the most significant given nondecimal signal of said source of signals being dimensioned to be one-half of the value of the least significant decimal number stage of said reversible counter, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said decimal signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said decimal signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal digit stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure.
Claim 6
Dependent Claim
212 words
A conversion device for converting a train of pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary-coded decimal number reversible counter for storing decimal digits in decimal stages thereof, a given nondecimal coded number register, an adder-subtracter, a source of multidigit signals in parallel form representing the multidigits of a conversion factor number, a source of a serial train of add and subtract pulses, said adder-subtracter having a plurality of binary stages, means for applying said train of pulses to only certain of the least significant stages of said adder-subtracter, means for applying said multidigit signals to the remaining binary stages of said adder-subtracter, said adder-subtracter responsive to said applied serial train of pulses and said applied signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure.
Claim 7
Dependent Claim
212 words
A conversion device for converting a train of pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary-coded decimal number reversible counter for storing decimal digits in decimal stages thereof, a given nondecimal coded number register, an adder-subtracter, a source of multidigit signals in parallel form representing the multidigits of a conversion factor number, a source of a serial train of add and subtract pulses, said adder-subtracter having a plurality of binary stages, means for applying said train of pulses to only certain of the least significant stages of said adder-subtracter, means for applying said multidigit signals to the remaining binary stages of said adder-subtracter, said adder-subtracter responsive to said applied serial train of pulses and said applied signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure.
Claim 8
Dependent Claim
283 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary-coded decimal number reversible counter for storing decimal numbers in decimal number stages thereof, a binary-coded number register, a binary number adder-subtracter, a source of binary signals in parallel form representing the multidigits of a conversion factor number, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said binary signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said binary signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal number stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure, the stages of said adder-subtracter circuit comprising flip-flop logic circuit means having a train of input signal pulses supplied to the input thereof, an input network of interconnected NOT-AND and OR-NOT logic circuit means for supplying to the steering input of the flip-flop logic circuit means said binary signals representative of the value of the conversion factor number to be added or subtracted at a given stage and any carry or borrow values to be processed from adjacent stages, and an output network of interconnected NOT-AND and OR-NOT logic circuit means for deriving any output carry or borrow value signal for supply to adjacent stages.
Claim 9
Dependent Claim
283 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary-coded decimal number reversible counter for storing decimal numbers in decimal number stages thereof, a binary-coded number register, a binary number adder-subtracter, a source of binary signals in parallel form representing the multidigits of a conversion factor number, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said binary signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said binary signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal number stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure, the stages of said adder-subtracter circuit comprising flip-flop logic circuit means having a train of input signal pulses supplied to the input thereof, an input network of interconnected NOT-AND and OR-NOT logic circuit means for supplying to the steering input of the flip-flop logic circuit means said binary signals representative of the value of the conversion factor number to be added or subtracted at a given stage and any carry or borrow values to be processed from adjacent stages, and an output network of interconnected NOT-AND and OR-NOT logic circuit means for deriving any output carry or borrow value signal for supply to adjacent stages.
Claim 10
Dependent Claim
319 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary coded decimal number reversible counter for storing decimal numbers in decimal number stages thereof, a binary-coded number register, a binary number adder-subtracter, a source of binary signals in parallel form representing the multidigits of a conversion factor number, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said binary signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said binary signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal number stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure, only certain of the least significant stages of the adder-subtracter circuit means having adjustable value binary signals supplied thereto and the remaining stages having fixed value binary signals supplied thereto and the stages of the adder-subtracter circuit having the adjustable signals supplied thereto comprise flip-flop logic circuit means having a train of input signal pulses supplied to the input thereof, an input network of interconnected NOT-AND and OR-NOT logic circuit means for supplying to the steering input of the flip-flop logic circuit means binary signals representative of the value of the conversion factor to be added or subtracted at a given stage and any carry or borrow values to be processed from adjacent stages, and an output network of interconnected NOT-AND and OR-NOT logic circuit means for deriving any output carry or borrow value signal for supply to adjacent stages.
Claim 11
Dependent Claim
319 words
A conversion device for converting a train of interferometer fringe count pulses indicative of a measurement in nonstandard units into a measurement in standard units comprising: a binary coded decimal number reversible counter for storing decimal numbers in decimal number stages thereof, a binary-coded number register, a binary number adder-subtracter, a source of binary signals in parallel form representing the multidigits of a conversion factor number, a source of a serial train of add and subtract pulses, said adder-subtracter responsive to said serial train of pulses and to said binary signals for adding in parallel to or subtracting in parallel from the number stored in said register the conversion factor number represented by said binary signals for each pulse in said train of pulses, said register dimensioned to supply its overflow count in series to the least significant decimal number stage of said counter as a decimal unit incremental input, said counter responsive to said supplied overflow counts for presenting the number represented by the algebraic summation of said pulses in said train in said standard units of measure, only certain of the least significant stages of the adder-subtracter circuit means having adjustable value binary signals supplied thereto and the remaining stages having fixed value binary signals supplied thereto and the stages of the adder-subtracter circuit having the adjustable signals supplied thereto comprise flip-flop logic circuit means having a train of input signal pulses supplied to the input thereof, an input network of interconnected NOT-AND and OR-NOT logic circuit means for supplying to the steering input of the flip-flop logic circuit means binary signals representative of the value of the conversion factor to be added or subtracted at a given stage and any carry or borrow values to be processed from adjacent stages, and an output network of interconnected NOT-AND and OR-NOT logic circuit means for deriving any output carry or borrow value signal for supply to adjacent stages.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |