Credit card verifier apparatus

Claim 2

A unitary station indicia verification apparatus for comparing an identification indicia with a stored list of indicia, said apparatus comprising: a. means for introducing an identification indicia for comparison into said apparatus, b. a shift register having a plurality of bistable storage elements for receiving the identification indicia introduced into said apparatus, c. storage means for retaining a list of stored indicia with which said identification indicia is to be compared, d. storage reading means for reading the stored indicia, e. recirculating means for recirculating the introduced identification indicia in said shift register, f. means for introducing clock pulses to compare the identification indicia with the stored indicia external to the recirculating means on a time basis, g. means for serially comparing the identification indicia during recirculation in said shift register with the stored indicia on a bit-by-bit basis, h. and advisory signal means operatively connected to said last named means for being actuated and render an advisory signal when the desired comparison or lack thereof occurs.

Claim 3

a head supporting frame operatively mounted on said base means,

Claim 4

a head supporting frame operatively mounted on said base means,

Claim 5

the indicia verification apparatus of claim 1 further characterized in that each identification indicia constitutes a word and includes a plurality of separate and distinct characters, each of said characters being generated into a set of plural bits upon introduction into said apparatus and each of the plural bits of a set being simultaneously introduced into said shift register, the stored indicia being in the form of a plurality of separate and distinct bits and being compared with the generated bits from the identification indicia.

Claim 6

The indicia verification apparatus of claim 2 further characterized in that said shift register comprises an entrance register capable of accommodating a set of bits generated by one indicia character, and a recirculating register capable of accommodating all of the bits generated by introduction of each of the characters of a word in said apparatus.

Claim 7

a data head operatively mounted on said head supporting frame,

Claim 8

a data head operatively mounted on said head supporting frame,

Claim 9

a synchronizing head operatively mounted on said base means,

Claim 10

a synchronizing head operatively mounted on said base means,

Claim 11

The indicia verification apparatus of claim 3 further characterized in that each set of indicia bits introduced into said entrance register is shifted into said recirculating register prior to introduction of the next set of plural bits into said entrance register.

Claim 12

The indicia verification apparatus of claim 4 further characterized in that recirculation and comparison is not initiated until all of the separate characters representing an identification word has been introduced into said shift register.

Claim 13

a trackway formed in saId base means for shiftably supporting said head supporting frame in a direction so that said data head moves sequentially past each of the tracks on the multitrack type, said trackway also being designed to enable said head supporting frame to shift toward said drum to a reading position and away from said drum to a remote position,

Claim 14

a trackway formed in saId base means for shiftably supporting said head supporting frame in a direction so that said data head moves sequentially past each of the tracks on the multitrack type, said trackway also being designed to enable said head supporting frame to shift toward said drum to a reading position and away from said drum to a remote position,

Claim 15

ratchet-type means on said base means for intermittently shifting said head supporting means along said base means so that said data head is sequentially positioned on each next adjacent track of said tape,

Claim 16

ratchet-type means on said base means for intermittently shifting said head supporting means along said base means so that said data head is sequentially positioned on each next adjacent track of said tape,

Claim 17

The indicia verification apparatus of claim 4 further characterized in that a bit counter is operatively associated with said shift register for counting the plural bits representing each character.

Claim 18

The indicia verification apparatus of claim 6 further characterized in that the apparatus comprises means for generating a series of sequentially available shift pulses, and means operatively connecting said last named means to said bit counter for shifting each set of bits further into said recirculating register by means of sequentially allocated shift pulses and thereby allow space in said shift register for the next set of bits.

Claim 19

a stepping solenoid operatively mounted on said base means for actuating said ratchet-type means,

Claim 20

a stepping solenoid operatively mounted on said base means for actuating said ratchet-type means,

Claim 21

means operatively associated with said stepping solenoid for enabling shifting movement of said head supporting frame to a reading position and to a remote position,

Claim 22

means operatively associated with said stepping solenoid for enabling shifting movement of said head supporting frame to a reading position and to a remote position,

Claim 23

The indicia verification apparatus of claim 2 further characterized in that said storage means contains stored logic data and that the storage reading means reads the logic data along with the stored indicia.

Claim 24

resetting means on said base means for disengaging said ratchet-type means to shift said head supporting frame to its initial position after said data head has read each of the tracks on said multitrack tape, i. clock pulse means operatively connected to said synchronizing head for generation of a series of said clock pulses from said synchronizing pulses, j. a head position gate operatively connected to said clock pulse means and being operatively connected to said stepping solenoid for enabling actuation thereof, k. a shift pulse gate operatively connected to said head position gate and to said shift gate and 4-bit counter for generating shift pulses and enabling said four bit counter to pass four shift pulses through said shift gate to shift each 4-binary decimal code bits representing each character into said recirculating register, l. camming means operatively associated with said drum causing generating of a cam pulse with each revolution of said drum, m. a track shift mechanism operatively connected to said head position gate and causing actuation of said head carriage mechanism to shift said data head to the next adjacent track on said tape after each complete revolution of said drum, n. a filter connected to said data head and being capable of sorting logic pulses from said data bits, o. a bit comparison device operatively connected to said filter, p. load gates operatively interposed between said entrance register and said recirculating register and preventing shifting action in said shift register during loading of four bits in said entrance register, q. recirculating control gates operatively connected to the output of said recirculating register and preventing recirculation of the information contained therein during the information entrance process, r. means connecting said recirculating control gates to said comparison mechanism to compare the data bits read from said tape with the recirculating bits from said recirculating register, s. a memory device connected to the output of said comparison device for keeping track of all comparisons and lack thereof, t. means actuable upon the coincidence or lack thereof of all elements of said identification number with the stored list of invalid credit card numbers, u. and advisory signal means energizable by said last named means to advise of the presence of an invalid credit card.

Claim 25

resetting means on said base means for disengaging said ratchet-type means to shift said head supporting frame to its initial position after said data head has read each of the tracks on said multitrack tape, i. clock pulse means operatively connected to said synchronizing head for generation of a series of said clock pulses from said synchronizing pulses, j. a head position gate operatively connected to said clock pulse means and being operatively connected to said stepping solenoid for enabling actuation thereof, k. a shift pulse gate operatively connected to said head position gate and to said shift gate and 4-bit counter for generating shift pulses and enabling said four bit counter to pass four shift pulses through said shift gate to shift each 4-binary decimal code bits representing each character into said recirculating register, l. camming means operatively associated with said drum causing generating of a cam pulse with each revolution of said drum, m. a track shift mechanism operatively connected to said head position gate and causing actuation of said head carriage mechanism to shift said data head to the next adjacent track on said tape after each complete revolution of said drum, n. a filter connected to said data head and being capable of sorting logic pulses from said data bits, o. a bit comparison device operatively connected to said filter, p. load gates operatively interposed between said entrance register and said recirculating register and preventing shifting action in said shift register during loading of four bits in said entrance register, q. recirculating control gates operatively connected to the output of said recirculating register and preventing recirculation of the information contained therein during the information entrance process, r. means connecting said recirculating control gates to said comparison mechanism to compare the data bits read from said tape with the recirculating bits from said recirculating register, s. a memory device connected to the output of said comparison device for keeping track of all comparisons and lack thereof, t. means actuable upon the coincidence or lack thereof of all elements of said identification number with the stored list of invalid credit card numbers, u. and advisory signal means energizable by said last named means to advise of the presence of an invalid credit card.

Claim 26

A unitary station indicia identification apparatus for comparing an identification indicia in the form of a word having a plurality of separate characters with a stored list of indicia in the form of binary-type bits, said apparatus comprising: a. input means for introducing each of the characters into said apparatus and converting each of the characters into a set of binary-type indicia bits, b. a recirculating shift register having a number of bistable elements sufficient to accommodate the indicia bits representative of all of the characters in a word, c. means for introducing each set of binary-type indicia bits representative of the word of said identification indicia into said recirculating register, d. a binary-type bit counter, e. shift pulse generating means operatively connected to said bit counter and said shift register for further shifting each of the sets introduced into the shift register a set at a time, said bit counter allocating a number of shift pulses equivalent to the number of indicia binary-type bits in each set, f. data storage means having a magnetic member with stored binary-type bits and logic pulses, g. reading means for detecting and reading the stored binary-type bits, h. motive means for causing relative movement between said magnetic member and reading means to enable the reading of the stored binary-type bits and logic pulses in said data storage means, i. means for initiating recirculation and serial comparison of the binary-type bits representative of said identification indicia during recirculation with the stored binary-type bits representative of said stored list of indicia on a bit-by-bit basis, said comparison being performed external to said shift register, j. memory means for maintaining a memory of equality of any of the binary type bits representative of the identification indicia with the stored binary type bits during the serial comparison thereof, k. coincidence indication means operatively connected to said memory means and actuable upon the coincidence or lack thereof of all of the stored binary-type bits with the binary-type bits representative of said identification indicia, l. and advisory signal means operatively connected to said last-named means and energizable thereby upon detection of a valid or invalid identification indicia.

Claim 27

A unitary station indicia identification apparatus for comparing an identification indicia in the form of a word having a plurality of separate characters with a stored list of indicia in the form of binary-type bits, said apparatus comprising: a. input means for introducing each of the characters into said apparatus and converting each of the characters into a set of binary-type indicia bits, b. a recirculating shift register having a number of bistable elements sufficient to accommodate the indicia bits representative of all of the characters in a word, c. means for introducing each set of binary-type indicia bits representative of the word of said identification indicia into said recirculating register, d. a binary-type bit counter, e. shift pulse generating means operatively connected to said bit counter and said shift register for further shifting each of the sets introduced into the shift register a set at a time, said bit counter allocating a number of shift pulses equivalent to the number of indicia binary-type bits in each set, f. data storage means having a magnetic member with stored binary-type bits and logic pulses, g. reading means for detecting and reading the stored binary-type bits, h. motive means for causing relative movement between said magnetic member and reading means to enable the reading of the stored binary-type bits and logic pulses in said data storage means, i. means for initiating recirculation and serial comparison of the binary-type bits representative of said identification indicia during recirculation with the stored binary-type bits representative of said stored list of indicia on a bit-by-bit basis, said comparison being performed external to said shift register, j. memory means for maintaining a memory of equality of any of the binary type bits representative of the identification indicia with the stored binary type bits during the serial comparison thereof, k. coincidence indication means operatively connected to said memory means and actuable upon the coincidence or lack thereof of all of the stored binary-type bits with the binary-type bits representative of said identification indicia, l. and advisory signal means operatively connected to said last-named means and energizable thereby upon detection of a valid or invalid identification indicia.

Claim 28

The indicia identification apparatus of claim 9 further characterized in that an entrance register is operatively associated with the recirculating register and the input means, said entrance register having a sufficient number of bistable elements to accommodate all of the binary-type bits of a set and all of the bits of a set being introduced in parallel into said entrance register prior to introduction into said recirculating register.

Claim 29

The indicia identification apparatus of claim 10 further characterized in that recirculation control means is operatively associated with said recirculating register to prevent recirculation during introduction of all of the sets into said recirculating register.

Claim 30

The indicia identification apparatus of claim 10 further characterized in that load gate means is operatively interposed between said entrance register and said recirculating register to control the shifting of the bits in said entrance register into said recirculating register.

Claim 31

The indicia identification apparatus of claim 9 further characterized in that an AND gate matrix is operatively connected to said input means and said recirculating shift register, all of the bits of a set being introduced in parallel into said AND gate matrix prior to introduction into said recirculating register.

Claim 32

The indicia identification apparatus of claim 13 further characterized in that an AND gate is provided for each bit and that all of the AND gates are connected to an OR gate.

Claim 33

The indicia identification apparatus of claim 10 further characterized in that capacitors are interposed in the means for introducing the indicia bits into the entrance register.

Claim 34

The indicia identification apparatus of claim 9 further characterized in that said bit counter comprises means for selectively metering a number of count pulses equivalent to the number of bits in a set and enabling said shift pulse generating means to shift just the number of bits of a set into the first equivalent number of flip-flops in said recirculating register.

Claim 35

The indicia identification apparatus of claim 9 further characterized in that said comparison means comprises a half adder and a memory flip-flop to keep track of all coincidence between indicia bits and stored bits.

Claim 36

The indicia identification apparatus of claim 9 further characterized in that a latching circuit is operatively connected to said coincidence indication means and said advisory signal means for holding said advisory signal means in the energized state upon actuation of said coincidence indication means until resetting of the apparatus.

Claim 37

The indicia identification aPparatus of claim 9 further characterized in that means for generating sync pulses is provided and is operatively connected to said reading means and to said coincidence indication means to provide comparison at sync pulse time.

Claim 38

The indicia identification apparatus of claim 19 further characterized in that the means for generating sync pulses comprises a track on said magnetic member containing sync pulses, and a sync reading head to read said sync pulses upon relative movement between said sync reading head and magnetic member.

Claim 39

The indicia identification apparatus of claim 9 further characterized in that a data head forms part of said reading means and is engageable against said magnetic member and reads the stored bits and logic pulses thereon when relative movement is created, and filtering means operatively connected to said data head for separating the logic pulses from the stored bits to provide comparison of the stored bits and indicia bits at logic pulse time.

Claim 40

The indicia identification apparatus of claim 9 further characterized in that a parity circuit is operatively connected to said shift register for detecting the generation or loss of a bit in said shift register, and error signal means operatively connected to said parity circuit for advising of such generation or loss of a bit.

Claim 41

The indicia identification apparatus of claim 9 further characterized in that magnetic member is a multitrack member and the stored bits is recorded thereon in FSK form.

Claim 42

The indicia identification apparatus of claim 9 further characterized in that said member is a multitrack member and recorded with nonreturn to zero mark data and that said data head includes a pair of individual reading elements located on two adjacent tracks of said magnetic member, each of two adjacent tracks of said member having identical data recorded thereon, and means connected to each of said elements for detecting a coincidence of reading on each of the two adjacent tracks having identical data recorded thereon.

Claim 43

The indicia identification apparatus of claim 9 further characterized in that said magnetic member also includes logic pulses which are interposed between each of the words recorded on said tape, and that comparison will occur between two logic pulses.

Claim 44

A credit card verification apparatus for comparing an identification number on a credit card with a stored list of invalid credit card numbers, said apparatus comprising: a. an outer housing, b. means for introducing the characters forming the credit card number into said apparatus and converting each of the characters into a 4-bit binary decimal code, c. a shift register having an entrance register capable of receiving four bits representing a character of the identification number and a recirculating register capable of holding all of the bits representing all of the characters of said identification number, d. a 4-bit counter capable of counting four pulses, e. a shift gate operatively connected to said entrance register, f. a drum operatively mounted in said housing and being rotatable therein, g. means on said drum for removably receiving a multitrack magnetic tape having stored lists of invalid credit card numbers recorded thereon in the form of stored binary coded decimal bits, said multitrack tape also having logic pulse signals stored thereon and being placed between a number of binary coded decimal bits equivalent to the number of bits generated by a decimal indicia character, said tape having a track containing synchronizing pulses, h. a head carriage mechanism operatively mounted in said outer housing, said head carriage mechanism comprising:

Claim 45

A credit card verification apparatus for comparing an identification number on a credit card with a stored list of invalid credit card numbers, said apparatus comprising: a. an outer housing, b. means for introducing the characters forming the credit card number into said apparatus and converting each of the characters into a 4-bit binary decimal code, c. a shift register having an entrance register capable of receiving four bits representing a character of the identification number and a recirculating register capable of holding all of the bits representing all of the characters of said identification number, d. a 4-bit counter capable of counting four pulses, e. a shift gate operatively connected to said entrance register, f. a drum operatively mounted in said housing and being rotatable therein, g. means on said drum for removably receiving a multitrack magnetic tape having stored lists of invalid credit card numbers recorded thereon in the form of stored binary coded decimal bits, said multitrack tape also having logic pulse signals stored thereon and being placed between a number of binary coded decimal bits equivalent to the number of bits generated by a decimal indicia character, said tape having a track containing synchronizing pulses, h. a head carriage mechanism operatively mounted in said outer housing, said head carriage mechanism comprising:

Claim 46

The credit card verification apparatus of claim 26 further characterized in that a read error circuit is connected to said filter and is capable of determining an error in the reading of data from said tape, and error advisory signal means operatively connected to said read error circuit and being energizable upon detection of an error in the reading process.

Claim 47

The credit card verification apparatus of claim 26 further characterized in that said filter has a ''''one'''' level output, a ''''zero'''' level output and a logic pulse output, and that said read error circuit comprises an exclusive OR gate connected to the ''''one'''' and ''''zero'''' level outputs of said filter and an AND gAte connected to the output of said OR gate.

Claim 48

The credit card verification apparatus of claim 27 further characterized in that the means for introducing the elements of the credit card member into said apparatus comprises a keyboard mounted on said apparatus with a diode matrix connected to the keyboard for converting each of the elements into a 4-bit binary decimal code.

Claim 49

The credit card verification apparatus of claim 26 further characterized in that the means for introducing the elements of the credit card number into said apparatus comprises an automatic card reader which includes: a. a card receiving tray capable of carrying said credit card into said housing, b. motive means for moving said tray, c. a light source capable of directing light on a bar code appearing on said credit card, d. light sensitive photocells for detecting the amount of light reflected from photocells, e. circuit means for converting the reflected light from the bar code into a 5-bit code representative of the elements designated by said bar code, f. a conversion matrix operatively connected to said circuit means for converting the 5-bit code into a 4-bit code, g. and a settling time circuit for insuring proper reading of said bar code.

Claim 50

The credit card verification apparatus of claim 30 further characterized in that a parity circuit is operatively connected to said shift register for detecting the generation or loss of a bit in said shift register, and error signal means operatively connected to said parity circuit for advising of such generation or loss of a bit.

Claim 51

The credit card verification apparatus of claim 31 further characterized in that said parity circuit comprises: a. a first counter for counting the number of pulses passing into said recirculating register from said entrance register, b. a second counter for counting the number of pulses recirculated in said recirculating register, c. An exclusive OR circuit for counting the number of pulses jammed into said entrance register, d. and detection means operatively connected to each of said first and second counters and said exclusive OR gate and to said error signal means.

Claim 52

The credit card verification apparatus of claim 26 further characterized in that said tape is recorded with nonreturn to zero mark data and that said data head includes a pair of individual reading elements located on two adjacent tracks, each of two adjacent tracks of said tape having identical data recorded thereon, and means connected to each of said elements for detecting a coincidence of reading on each of the two adjacent tracks having identical data recorded thereon.

Claim 53

The process of comparing identification indicia with a stored list of indicia in a unitary station, said process comprising: a. generating binary decimal bits which are representative of the identification indicia, b. reading the stored list of indicia, c. detecting synchronous pulses simultaneously with the reading of the stored list of indicia, d. circulating the binary decimal bits, e. serially comparing the binary decimal bits with the stored indicia on a bit-by-bit basis on a synchronous time basis and during circulation of the binary decimal bits, f. and generating a responsive action when a comparison or lack thereof is detected.

Claim 54

The process of comparing identification indicia with a stored list of indicia in a unitary station, said process comprising: a. generating binary decimal bits which are representative of the identification indicia, b. reading the stored list of indicia, c. detecting synchronous pulses simultaneously with the reading of the stored list of indicia, d. circulating the binary decimal bits, e. serially comparing the binary decimal bits with the stored indicia on a bit-by-bit basis on a synchronous time basis and during circulation of the binary decimal bits, f. and generating a responsive action when a comparison or lack thereof is detected.

Claim 55

The process of comparing identification indicia with a stored list of indicia in the form of stored list indicia bits on a multitrack magnetic element in an apparatus including a shift register capable of causing recirculation, and a data head for reading indicia and a sync head for reading sync pulses, said process comprising: a. generating a set of binary decimal bits for each element in the identification indicia, b. inserting each set of generated bits into the shift register, c. generating a number of shift pulses which are equivalent to the number of bits in each set for shiftiNg said set into said shift register and allowing room for the next succeeding set of bits, d. inhibiting recirculating during the entrance of each of the sets into the shift register, e. shifting the data head into contact with a track of the magnetic element causing reading of the stored list of indicia bits, f. recirculating the generated bits in said shift register after all of the sets representing each of the elements in said identification indicia have been entered into said shift register, g. adding the generated data bits to the stored indicia bits and serially comparing said bits on a bit-by-bit basis, h. reading said sync pulses to make said comparison on a sync time basis, i. and providing an advisory signal after reading all of the data on said element when a comparison or lack thereof is detected.

Claim 56

The process of comparing identification indicia with a stored list of indicia in the form of stored list indicia bits on a multitrack magnetic element in an apparatus including a shift register capable of causing recirculation, and a data head for reading indicia and a sync head for reading sync pulses, said process comprising: a. generating a set of binary decimal bits for each element in the identification indicia, b. inserting each set of generated bits into the shift register, c. generating a number of shift pulses which are equivalent to the number of bits in each set for shiftiNg said set into said shift register and allowing room for the next succeeding set of bits, d. inhibiting recirculating during the entrance of each of the sets into the shift register, e. shifting the data head into contact with a track of the magnetic element causing reading of the stored list of indicia bits, f. recirculating the generated bits in said shift register after all of the sets representing each of the elements in said identification indicia have been entered into said shift register, g. adding the generated data bits to the stored indicia bits and serially comparing said bits on a bit-by-bit basis, h. reading said sync pulses to make said comparison on a sync time basis, i. and providing an advisory signal after reading all of the data on said element when a comparison or lack thereof is detected.

Claim 57

The process of claim 35 further characterized in that a head shift pulse is generated after each track has been read by said data head, and shifting said head to the next track on said element by means of said head shift pulse.

Claim 58

The process of claim 36 further characterized in that the process includes the determination of the last track on said element read by said data head, and stopping the process after the last track has been entirely read.

Claim 59

The process of claim 35 further characterized in that logic pulses are recorded with said stored list of indicia bits and are read with the indicia bits by the data head.

Claim 60

A unitary station apparatus for comparing an unknown indicia with a stored list of indicia, said apparatus comprising: a. a shift register for receiving the unknown indicia in the form of a plurality of digital-type bits in binary format introduced into said apparatus, b. storage means operatively associated with said apparatus for retaining the stored list of indicia in the form of digital-type bits in binary format, c. recirculating means operatively associated with said shift register for recirculating the digital-type bits of the unknown indicia in said shift register, d. means operatively connected to said recirculating means for serially comparing the digital-type bits of said known indicia bit by bit with the digital-type bits of said stored list of indicia during recirculation of the digital-type bits of the unknown indicia in said shift register on a pulse timed basis, said comparison being performed external to said shift register, and e. means operatively connected to said last named means and being responsive to comparison or lack thereof.

Claim 61

A unitary station apparatus for comparing an unknown indicia with a stored list of indicia, said apparatus comprising: a. a shift register for receiving the unknown indicia in the form of a plurality of digital-type bits in binary format introduced into said apparatus, b. storage means operatively associated with said apparatus for retaining the stored list of indicia in the form of digital-type bits in binary format, c. recirculating means operatively associated with said shift register for recirculating the digital-type bits of the unknown indicia in said shift register, d. means operatively connected to said recirculating means for serially comparing the digital-type bits of said known indicia bit by bit with the digital-type bits of said stored list of indicia during recirculation of the digital-type bits of the unknown indicia in said shift register on a pulse timed basis, said comparison being performed external to said shift register, and e. means operatively connected to said last named means and being responsive to comparison or lack thereof.

Claim 62

A unitary station apparatus for comparing an unknown indicia with a stored list of indicia, said apparatus comprising: a. drum-type retaining means in said apparatus for retaining a magnetic tapelike element, b. a magnetic tapelike element removably disposed on said retaining means so that the terminal ends of said tapelike element are nonoverlapping for any substantial distance, said tapelike element containing the stored list of indicia in the form of a plurality of digital-type bits in binary format, d. means in said apparatus for converting the unknown indicia to a plurality of digital-type bits in binary format, e. means in said apparatus for reading the digital type bits representing said unknown indicia from said tape and serially comparing said unknown indicia digital-type bits with the digital-type bits representing said stored indicia on a bit-by-bit basis, and f. and means operatively connected to said last-named means and being responsive to comparison or lack thereof.

Claim 63

A unitary station apparatus for comparing an unknown indicia with a stored list of indicia, said apparatus comprising: a. drum-type retaining means in said apparatus for retaining a magnetic tapelike element, b. a magnetic tapelike element removably disposed on said retaining means so that the terminal ends of said tapelike element are nonoverlapping for any substantial distance, said tapelike element containing the stored list of indicia in the form of a plurality of digital-type bits in binary format, d. means in said apparatus for converting the unknown indicia to a plurality of digital-type bits in binary format, e. means in said apparatus for reading the digital type bits representing said unknown indicia from said tape and serially comparing said unknown indicia digital-type bits with the digital-type bits representing said stored indicia on a bit-by-bit basis, and f. and means operatively connected to said last-named means and being responsive to comparison or lack thereof.

Claim 64

A unitary station indicia comparison apparatus for comparing an unknown indicia with a stored indicia, said apparatus comprising a logic pulse source, a shift register having a plurality of flip-flops divided into an entrance register and a recirculating register and where indicia to be compared is introduced into said entrance register in the form of binary bits and is passed into said recirculating regisTer for recirculation therethrough, storage means for retaining a stored list of indicia, a parity circuit including a first counter connected to the input of the entrance register and counting the number of pulses recirculated in said recirculating register, a second counter connected to the first counter and to each of the flip-flops in said entrance register and recirculating register for counting the number of pulses shifted into said recirculating register from said entrance register, an exclusive OR circuit connected to the inputs of each of the flip-flops in said entrance register for examining the pulses entered into said entrance register, said OR circuit being operatively connected to the input of said second counter, means for connecting said first counter to said logic pulse source to provide counting at logic pulse time, a comparison gate being connected to said first and second counters and to said logic pulse source for detecting gain or loss of a pulse in said shift register at logic pulse time, means operatively associated with said shift register for comparing said known indicia bit by bit with said stored list of indicia on a pulse time basis, and means operatively connected to said last named means and being responsive to comparison or lack thereof.

Claim 65

A unitary station indicia comparison apparatus for comparing an unknown indicia with a stored indicia, said apparatus comprising a logic pulse source, a shift register having a plurality of flip-flops divided into an entrance register and a recirculating register and where indicia to be compared is introduced into said entrance register in the form of binary bits and is passed into said recirculating regisTer for recirculation therethrough, storage means for retaining a stored list of indicia, a parity circuit including a first counter connected to the input of the entrance register and counting the number of pulses recirculated in said recirculating register, a second counter connected to the first counter and to each of the flip-flops in said entrance register and recirculating register for counting the number of pulses shifted into said recirculating register from said entrance register, an exclusive OR circuit connected to the inputs of each of the flip-flops in said entrance register for examining the pulses entered into said entrance register, said OR circuit being operatively connected to the input of said second counter, means for connecting said first counter to said logic pulse source to provide counting at logic pulse time, a comparison gate being connected to said first and second counters and to said logic pulse source for detecting gain or loss of a pulse in said shift register at logic pulse time, means operatively associated with said shift register for comparing said known indicia bit by bit with said stored list of indicia on a pulse time basis, and means operatively connected to said last named means and being responsive to comparison or lack thereof.

Claim 66

The indicia comparison apparatus of claim 41 further characterized in that a one-shot is interposed in the means connecting the first counter to said logic pulse source for delaying the resetting action of said first counter until a comparison has been made in the comparison gate.

Claim 67

The indicia comparison apparatus of claim 41 further characterized in that the exclusive OR circuit comprises an exclusive OR gate connected to the input of each of two flip-flops in said entrance register and a final exclusive OR gate connected to the outputs of each of the aforementioned exclusive OR gates.

Claim 70

The apparatus of claim 44 further characterized in that said radiation emitting means is a visible light source and said radiation sensitive resistance means are a series of light sensitive photocells, the resistance characteristics of which change responsive to the light incident thereon.

Claim 71

The apparatus of claim 44 further characterized in that an imprinting member is located in the path of movement of the retaining member for imprinting the information on the code bearing element onto a second eleMent disposed in facewise engagement with said code bearing element.