Digital recording-playback technique

Claim 2

In a return-to-zero type of digital playback apparatus having a shift register for storing a first train of positive-going and negative-going sets of pulses received from a recording medium in series form followed by a synchronizing pulse, an output register, and gating means for transferring data stored in said shift register to said output register in parallel form in response to said synchronizing signal, the improvement comprising: a. separator means for separating said positive-going, negativegoing and synchronizing pulses; b. inverting means connected to said separator means for inverting signals of one polarity developed by said separator means; c. adding means connected to said separator means and to said inverting means for providing a second train of pulses all of one polarity and equal in number of pulses to the sum of said positive-going and negative-going pulses; d. counter means connected to receive said second train of pulses and for providing a plurality of output signals each indicative of said number of pulses; and e. logic means responsive to at least one of said output signals to open said gating means when a selected one of said plurality of output signals is received substantially in coincidence with said synchronizing signal.

Claim 3

The apparatus of claim 1, wherein said counter means is a ring counter.

Claim 4

The apparatus of claim 1, wherein said logic means comprises an AND gate.

Claim 5

The apparatus of claim 1, wherein said counter means is a ring counter, and said logic means comprises an NAND gate.

Claim 6

the apparatus of claim 1, wherein said counter means is a ring counter, and said logic means comprises NAND gate followed by a NOR gate.

Claim 7

In a digital recording-playback apparatus having storage means for storing a train of pulse signals comprised of a plurality of binary ''''1'''' and binary ''''0'''' pulse signals received from a recording medium in series form, followed by a synchronizing pulse; an output register; and gating means for transferring data stored in said storage means to said output register in parallel form in response to the receipt of a said synchronizing signal; the improvement comprising: a. first separator circuit means connected to recEive said train of binary ''''1'''' and binary ''''0'''' pulse signals for, upon the receipt of a plurality of binary ''''1'''' pulse signals, developing a corresponding number of first output pulse signals; b. second separator circuit means connected to receive said train of binary ''''1'''' and binary ''''0'''' pulse signals for, upon the receipt of a plurality of binary ''''0'''' pulse signals, developing a corresponding number of second output pulse signals, c. adding circuit means connected to receive said first and second output pulse signals for providing a train of control pulse signals corresponding in number to the sum of said first and second output pulse signals; d. counter means connected to receive said train of control pulse signals for developing an actuator signal upon the receipt of a predetermined number of control pulse signals; and, e. logic means responsive to said output signal developed by said counter means to actuate said gating means when said actuator signal is received substantially in coincidence with a said synchronizing signal.

Claim 8

In a digital recording-playback apparatus having storage means for storing a train of pulse signals comprised of a plurality of binary ''''1'''' and binary ''''0'''' pulse signals received from a recording medium in series form, followed by a synchronizing pulse; an output register; and gating means for transferring data stored in said storage means to said output register in parallel form in response to the receipt of a said synchronizing signal; the improvement comprising: a. first separator circuit means connected to recEive said train of binary ''''1'''' and binary ''''0'''' pulse signals for, upon the receipt of a plurality of binary ''''1'''' pulse signals, developing a corresponding number of first output pulse signals; b. second separator circuit means connected to receive said train of binary ''''1'''' and binary ''''0'''' pulse signals for, upon the receipt of a plurality of binary ''''0'''' pulse signals, developing a corresponding number of second output pulse signals, c. adding circuit means connected to receive said first and second output pulse signals for providing a train of control pulse signals corresponding in number to the sum of said first and second output pulse signals; d. counter means connected to receive said train of control pulse signals for developing an actuator signal upon the receipt of a predetermined number of control pulse signals; and, e. logic means responsive to said output signal developed by said counter means to actuate said gating means when said actuator signal is received substantially in coincidence with a said synchronizing signal.

Claim 9

An apparatus as defined in claim 6 wherein said storage means includes a shift register; and, inverting circuit means connected to said first separator circuit means for inverting said first output pulse signals so that said first and second signals are of the same polarity.

Claim 10

An apparatus as defined in claim 7 wherein said counter means includes a shift register for developing a plurality of actuator signals each indicative of a different predetermined number of control pulse signals, and logic means including circuit means for actuating said gating means when a selected one of said plurality of signals is received substantially in coincidence with a said synchronizing signal.