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US3601710A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital detector for binary fsk signaling

Assignee: AT&T Inc
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Filing: 1969-08-22
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Granted: 1971-08-24
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Expires: 1989-08-22
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Abstract

Abstract A digital detector for a synchronous, low bit-rate signaling systems comprises monostable timing devices and logic components to replace the low-pass filter and slicer circuits of the conventional zero-crossing detector. The detection scheme is dependent upon a comparison of zero-crossing intervals and an optimum threshold interval chosen to minimize synchronous distortion. The maximum theoretical bit rate is equal to the sum of the mark and space frequencies, corresponding to 50 percent peak synchronous distortion.

Inventors

  • 👤 Michael A Morra

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 15:53
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1563

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 104 words
A demodulator for deriving digital information from a continuous-phase, frequency-shift-modulated wave containing high and low frequencies representing respective complementary data bits comprising means for receiving said modulated wave, means for generating unidirectional pulses corresponding to the zero crossings of said received wave, and digital detection means responsive to said unidirectional pulses for producing said complementary data bits as determined by a comparison of successive zero-crossing intervals with an optimum threshold interval defined as the reciprocal of the sum of said high and low frequencies, said digital means producing said data bits as said zero-crossing intervals are greater or less than said optimum threshold interval.
Claim 2
Dependent Claim 104 words
A demodulator for deriving digital information from a continuous-phase, frequency-shift-modulated wave containing high and low frequencies representing respective complementary data bits comprising means for receiving said modulated wave, means for generating unidirectional pulses corresponding to the zero crossings of said received wave, and digital detection means responsive to said unidirectional pulses for producing said complementary data bits as determined by a comparison of successive zero-crossing intervals with an optimum threshold interval defined as the reciprocal of the sum of said high and low frequencies, said digital means producing said data bits as said zero-crossing intervals are greater or less than said optimum threshold interval.
Claim 3
Dependent Claim 58 words
The demodulator of claim 1 wherein said digital means further comprises timing means responsive to said unidirectional pulses for producing uniform pulses each having a duration equal to the reciprocal of the sum of said high and low frequencies, and logic means jointly responsive to said unidirectional pulses and said uniform pulses for producing said complementary data bits.
Claim 4
Dependent Claim 97 words
The demodulator of claim 2 wherein said timing means further comprises first monostable means responsive to said unidirectional pulses for producing a first series of uniform pulses each having a duration equal to less than one-half the reciprocal of said high frequency and second monostable means responsive to the termination of each of said first series of pulses for producing a second series of uniform pulses each having a duration equal to the difference between the duration of each of said first series of pulses and the reciprocal of the sum of said high and low frequencies.
Claim 5
Dependent Claim 19 words
The demodulator of claim 1 wherein said generating means comprises in tandem a limiter, a differentiator, and a rectifier.
Claim 6
Dependent Claim 209 words
A demodulator for deriving digital information from a continuous-phase, frequency-shift-modulated wave containing high and low frequencies representing respective complementary data bits comprising in combination means for receiving said modulated wave, a limiter for squaring said modulated wave, a differentiator of said squared wave for producing alternate positive and negative pulses, a rectifier of said alternate pulses for producing unidirectional pulses corresponding to the zero crossings of said received wave, a first monopulser responsive to said unidirectional pulses for producing a first series of uniform pulses each having a duration equal to less than one-half the reciprocal of said high frequency, a second monopulser responsive to said first series of pulses for producing a second series of pulses each having a duration equal to the difference between the reciprocal of the sum of said high and low frequencies and the duration of each of said first series of pulses, an inverter responsive to said second series of pulses for producing the inverse thereof, a first AND gate jointly responsive to said unidirectional pulses and to said inverse pulses, a second AND gate jointly responsive to said first and second series of pulses and a flip-flop jointly controlled by said first and second AND gates for producing said complementary data bits.
Claim 7
Dependent Claim 209 words
A demodulator for deriving digital information from a continuous-phase, frequency-shift-modulated wave containing high and low frequencies representing respective complementary data bits comprising in combination means for receiving said modulated wave, a limiter for squaring said modulated wave, a differentiator of said squared wave for producing alternate positive and negative pulses, a rectifier of said alternate pulses for producing unidirectional pulses corresponding to the zero crossings of said received wave, a first monopulser responsive to said unidirectional pulses for producing a first series of uniform pulses each having a duration equal to less than one-half the reciprocal of said high frequency, a second monopulser responsive to said first series of pulses for producing a second series of pulses each having a duration equal to the difference between the reciprocal of the sum of said high and low frequencies and the duration of each of said first series of pulses, an inverter responsive to said second series of pulses for producing the inverse thereof, a first AND gate jointly responsive to said unidirectional pulses and to said inverse pulses, a second AND gate jointly responsive to said first and second series of pulses and a flip-flop jointly controlled by said first and second AND gates for producing said complementary data bits.
Claim 8
Dependent Claim 109 words
A demodulator for deriving digital information from a continuous-phase, frequency-shift-modulated wave containing high and low frequencies representing respective complementary data bits comprising means for receiving said modulated wave, means for generating unidirectional pulses corresponding to the zero crossings of said received wave, means for comparing the time interval between consecutive ones of said unidirectional pulses with an optimum threshold interval defined as the reciprocal of the sum of said high and low frequencies, and logic means controlled by said comparing means for producing either of said complementary data bits as the time interval between consecutive ones of said unidirectional pulses is greater or less than said optimum threshold interval.
Claim 9
Dependent Claim 109 words
A demodulator for deriving digital information from a continuous-phase, frequency-shift-modulated wave containing high and low frequencies representing respective complementary data bits comprising means for receiving said modulated wave, means for generating unidirectional pulses corresponding to the zero crossings of said received wave, means for comparing the time interval between consecutive ones of said unidirectional pulses with an optimum threshold interval defined as the reciprocal of the sum of said high and low frequencies, and logic means controlled by said comparing means for producing either of said complementary data bits as the time interval between consecutive ones of said unidirectional pulses is greater or less than said optimum threshold interval.

References Cited (Backward Citations)

US2713677A Cited
US3437932A Cited
US3508136A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-08-23 1975-02-22 1975-08-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-08-23 1979-02-22 1979-08-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-08-23 1983-02-22 1983-08-24 $7700.00 Window Closed / Lapsed

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