Frequency to direct current converter

Claim 2

A frequency to direct current converter for connection between a source of input signals and a direct current utilization means for producing a direct current output signal, the magnitude of which is a direct measure of the frequency of the input signals; 1. means for producing a fixed output pulse for each input wave including a timing circuit for controlling the output of said converter comprising in combination: a. a first bistable logic circuit having an input terminal coupled to a source of input signals, an output terminal, and a reset terminal, said first bistable logic circuit being changed from a first state to a second state upon initiation of an input signal at said input terminal; b. a second bistable logic circuit having a first input terminal coupled to be responsive to the state of said first bistable logic circuit, a clock input terminal connection to an external source of timing pulses, and an output terminal, said second bistable circuit being enabled to change state from a first state to a second state when said first bistable logic circuit is in its second state, said second bistable logic circuit changing from a first state to a second state in response to a first timing pulse and returning to its first state in response to a succeeding timing pulse; and c. means coupling said second bistable logic circuit to said first bistable logic circuit for resetting said first bistable logic circuit to its first state when said second bistable logic circuit changes to its second state to produce thereby a fixed output pulses; 2. signal averaging circuit means coupled to the output of said timing circuit to produce a direct current signal in response to each of the fixed output pulses so That the amplitude of the direct current output signal from said averaging circuit means is proportional to the number of the fixed output pulses and consequently, a measure of the input signal frequency.

Claim 3

a second bistable logic circuit having a first input terminal coupled to be responsive to the state of said first bistable logic circuit, a clock input terminal for connection to an external source of timing pulses and an output terminal, said second bistable circuIt being enabled to change state when an input is applied to its input terminal in response to said first bistable logic circuit being in its second state, and said second bistable logic circuit changing from a first state to a second state in responsible to a first timing pulse and returning to its first state in response to a succeeding timing pulse; and

Claim 4

a second bistable logic circuit having a first input terminal coupled to be responsive to the state of said first bistable logic circuit, a clock input terminal for connection to an external source of timing pulses and an output terminal, said second bistable circuIt being enabled to change state when an input is applied to its input terminal in response to said first bistable logic circuit being in its second state, and said second bistable logic circuit changing from a first state to a second state in responsible to a first timing pulse and returning to its first state in response to a succeeding timing pulse; and

Claim 5

A timing circuit according to claim 1 in which the output terminal of said first bistable logic circuit is directly coupled to the input of said second bistable logic circuit, the output of said timing circuit being derived from the output terminal of said second bistable logic circuit.

Claim 6

signal averaging circuit means coupled to the output of said timing circuit to produce a direct current signal in response to each of the fixed output pulses so That the amplitude of the direct current output signal from said averaging circuit means is proportional to the number of the fixed output pulses and consequently, a measure of the input signal frequency.

Claim 7

signal averaging circuit means coupled to the output of said timing circuit to produce a direct current signal in response to each of the fixed output pulses so That the amplitude of the direct current output signal from said averaging circuit means is proportional to the number of the fixed output pulses and consequently, a measure of the input signal frequency.

Claim 8

means coupling said second bistable logic circuit to said first bistable logic circuit for returning said first bistable logic circuit to its first state when said second bistable logic circuit changes to its second state; b. a direct current shopper circuit for connection to an external source of potential, said chopper circuit being connected to be controlled by said timing circuit whereby the magnitude of its output potential is determined; and c. coupling means coupling the output of said chopper circuit to the direct current utilization means.

Claim 9

means coupling said second bistable logic circuit to said first bistable logic circuit for returning said first bistable logic circuit to its first state when said second bistable logic circuit changes to its second state; b. a direct current shopper circuit for connection to an external source of potential, said chopper circuit being connected to be controlled by said timing circuit whereby the magnitude of its output potential is determined; and c. coupling means coupling the output of said chopper circuit to the direct current utilization means.

Claim 10

A timing circuit according to claim 2 wherein said first and second bistable logic circuits comprise J-K flip-flops.

Claim 11

A frequency to direct current converter for connection between a source of input signals and a direct current utilization means for producing a direct current output signal the magnitude of which is a direct measure of the frequency of the input signals; means for producing a fixed output pulse for each input wave including a timing circuit for controlling the output of said converter comprising in combination: a. a first bistable logic circuit having an input terminal coupled to a source of input signals, an output terminal, and a reset terminal, said first bistable logic circuit being changed from a first state to a second state upon initiation of an input signal at said input terminal; b. a second bistable logic circuit having a first input terminal coupled to be responsive to the state of said first bistable logic circuit, a clock input terminal for connection to an external source of timing pulses and an output terminal, said second bistable circuit being enabled to change state from a first state to a second state when said first bistable logic circuit is in its second state, said second bistable logic circuit changing from a first state to a second state in response to a first timing pulse, and returning to its first state in response to a succeeding timing pulse and c. means coupling said second bistable logic circuit to said first bistable logic circuit for resetting said first bistable logic circuit to its first state when said second bistable logic circuit changes to its second state to produce fixed output pulses. d. A NAND gate having a first input terminal connected to the output terminal of said first bistable logic circuit, a second input terminal coupled to the external source of timing pulses and an output terminal; e. a counter having an input terminal connected to the output terminal of said NAND gate and an output terminal connected to the input terminal of said second bistable logic circuit, said NAND gate producing output pulses when said first bistable logic circuit is in its second state, and said counter providing an enabling input to said second bistable logic circuit a predetermined number of timing pulses after said first bistable logic circuit changes state in response to an input signal; and f. means coupled from said second bistable logic circuit to return said first bistable logic circuit to its original state when said second bistable logic circuit changes from its first state to its second state.

Claim 12

A frequency to direct current converter for connection between a source of input signals and a direct current utilization means for producing a direct current output signal the magnitude of which is a direct measure of the frequency of the input signals; means for producing a fixed output pulse for each input wave including a timing circuit for controlling the output of said converter comprising in combination: a. a first bistable logic circuit having an input terminal coupled to a source of input signals, an output terminal, and a reset terminal, said first bistable logic circuit being changed from a first state to a second state upon initiation of an input signal at said input terminal; b. a second bistable logic circuit having a first input terminal coupled to be responsive to the state of said first bistable logic circuit, a clock input terminal for connection to an external source of timing pulses and an output terminal, said second bistable circuit being enabled to change state from a first state to a second state when said first bistable logic circuit is in its second state, said second bistable logic circuit changing from a first state to a second state in response to a first timing pulse, and returning to its first state in response to a succeeding timing pulse and c. means coupling said second bistable logic circuit to said first bistable logic circuit for resetting said first bistable logic circuit to its first state when said second bistable logic circuit changes to its second state to produce fixed output pulses. d. A NAND gate having a first input terminal connected to the output terminal of said first bistable logic circuit, a second input terminal coupled to the external source of timing pulses and an output terminal; e. a counter having an input terminal connected to the output terminal of said NAND gate and an output terminal connected to the input terminal of said second bistable logic circuit, said NAND gate producing output pulses when said first bistable logic circuit is in its second state, and said counter providing an enabling input to said second bistable logic circuit a predetermined number of timing pulses after said first bistable logic circuit changes state in response to an input signal; and f. means coupled from said second bistable logic circuit to return said first bistable logic circuit to its original state when said second bistable logic circuit changes from its first state to its second state.

Claim 13

The timing circuit of claim 4 in which the output of said first bistable logic circuit comprises the output of said timing circuit.

Claim 14

A frequency to direct current converter for connection between a source of input signals and a direct current utilization means, comprising in combination: a. a timing circuit comprising:

Claim 15

A frequency to direct current converter for connection between a source of input signals and a direct current utilization means, comprising in combination: a. a timing circuit comprising:

Claim 16

A converter according to claim 6 in which the output terminal of said first bistable logic circuit is directly coupled to the input of said second bistable logic circuit, and said chopper circuit is coupled to the output terminal of said second bistable logic circuit to determine the output of said converter.