US3601535A
Expired / Lapsed
US
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Measurement of minimum of a series of time intervals
Assignee: AT&T Inc
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Filing: 1969-11-24
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Granted: 1971-08-24
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Expires: 1989-11-24
Abstract
Abstract The circuit uses digital technique to measure the minimum break (or make) interval over a series of telephone dial pulses. During the first break, clock pulses are serially counted in a binary coded decimal up-counter. At the end of the first break, the upcount is transferred as the same count to a binary coded reentrant decimal down-counter of the same count capacity as the up-counter; and, at the start of the next break, the up-counter is cleared to zero count. During the second (new) break, clock pulses are serially subtracted from the count in the down-counter while being serially counted in the up-counter. If any clock pulses cause the count in the down-counter to go from zero count to capacity count, further up-counting in the up-counter is stopped. After each new measured break, the up-counter contains the minimum of the old and new counts, the minimum count is transferred to the down-counter, the up-counter is cleared to zero count, and the process repeats. Visual display is provided of the minimum count by translation from clock pulse count in the down-counter to milliseconds.
Inventors
- 👤 Robert B Heick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:25
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/32; G; G04; G04F; G04F10/00; G04F10/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
201 words
Circuitry for measuring the minimum time interval between pairs of signals among a plurality of such pairs comprising: A. a source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of the two signals of each pair; B. a first pulse count register; C. a second pulse count register; D. means for causing pulses from the source to be counted in the first register during the first time interval between the signals of a first pair; E. means controlled by the later occurring signal of each pair for causing the second register to contain a starting pulse count equal to the pulse count then in the first register; F. means controlled by each pair of signals succeeding the first pair for subtracting source pulses from the starting pulse count in the second register during the time interval between the signals of such succeeding pair; G. and, means controlled by the second register during the time interval between the signals of such succeeding pair for causing the pulse count in the first register to equal the sum of all source pulses not exceeding the number required to reduce below zero the starting pulse count in the second register.
Claim 2
Dependent Claim
201 words
Circuitry for measuring the minimum time interval between pairs of signals among a plurality of such pairs comprising: A. a source of pulses recurring at a constant frequency substantially greater than the recurrence frequency of the two signals of each pair; B. a first pulse count register; C. a second pulse count register; D. means for causing pulses from the source to be counted in the first register during the first time interval between the signals of a first pair; E. means controlled by the later occurring signal of each pair for causing the second register to contain a starting pulse count equal to the pulse count then in the first register; F. means controlled by each pair of signals succeeding the first pair for subtracting source pulses from the starting pulse count in the second register during the time interval between the signals of such succeeding pair; G. and, means controlled by the second register during the time interval between the signals of such succeeding pair for causing the pulse count in the first register to equal the sum of all source pulses not exceeding the number required to reduce below zero the starting pulse count in the second register.
Claim 3
Dependent Claim
79 words
The invention defined in claim 1: A. wherein is provided means controlled by the earlier occurring signal of each pair for causing the pulse count in the first register to equal zero; B. and, wherein the means for causing the pulse count in the first register to equal the sum comprises means for causing the first register to count all source pulses not exceeding the number required to reduce below zero the starting pulse count in the second register.
Claim 4
Dependent Claim
75 words
The invention defined in claim 2 wherein: A. the second register comprises a down-counter responsive to each pulse transmitted thereto to reduce by one the pulse count therein; b. and, the means for subtracting source pulses from the starting pulse count in the second register comprises first gating means controlled by a pair of signals for allowing source pulses to be transmitted to the down-Counter during the time interval between the signals of the pair.
Claim 5
Dependent Claim
104 words
The invention defined in claim 3 wherein: A. the first register comprises an up-counter responsive to each pulse transmitted thereto to increase by one the pulse count therein; B. and, the means for causing the first register to count all source pulses not exceeding the number required to reduce below zero the starting pulse count in the second register comprises second gating means controlled by the down-counter during the time interval between the signals of a pair for allowing to be transmitted to the up-counter all source pulses not exceeding the number required to reduce below zero the starting pulse count in the down-counter.
Claim 6
Dependent Claim
57 words
The invention defined in claim 4 wherein: A. the down-counter includes means for providing a control signal upon the addition to the down-counter of a source pulse reducing below zero the pulse count therein; B. and, the second gating means is controlled by the control pulse to prevent further source pulses from being transmitted to the up-counter.
Claim 7
Dependent Claim
70 words
The invention defined in claim 5 wherein: A. the down-counter comprises a plurality of binary counting stages settable from zero pulse count to capacity pulse count upon the transmission thereto of a source pulse; B. and, the means for providing a control signal comprises a control signal generator controlled by the down-counter to generate the control signal whenever the down-counter is set from zero pulse count to capacity pulse count.
Claim 8
Dependent Claim
84 words
The invention defined in claim 6 wherein: A. the up-counter comprises a plurality of binary counting stages; B. and, the means for causing the second register to contain a starting pulse count equal to the pulse count then in the first register comprises a plurality of transfer gates connected between the down-counter and the up-counter and controlled by the later occurring signal of each pair to transfer to the down-counter as a starting pulse count therein the pulse count then existing in the up-counter.
Claim 9
Dependent Claim
24 words
The invention defined in claim 7 wherein the first gating means comprises a first gate connected between the source of pulses and the down-counter.
Claim 10
Dependent Claim
23 words
The invention defined in claim 8 wherein the second gating means comprises a second gate connected between the first gate and the up-counter.
Claim 11
Dependent Claim
61 words
The invention defined in claim 7 wherein the means for causing source pulses to be counted in the first register during the first time interval between a first pair of signals comprises means effective prior to measurement of time intervals for registering capacity pulse count in the up-counter by setting all stages thereof to binary values representing capacity decimal pulse counts.
Claim 12
Dependent Claim
62 words
The invention defined in claim 10 wherein the means for causing source pulses to be counted in the first register during the first time interval between a first pair of signals also comprises means effective prior to measurement of time intervals for registering capacity pulse count in the down-counter by setting all stages thereof to binary values representing capacity decimal pulse counts.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |