Rate/time computer

Claim 2

A rate/time computer for continuously registering monetary charges as a function of rate and time comprising: a. a master unit with a master totalizing register; b. pulse generating means adapted to provide electrical pulses at a plurality of frequencies, each frequency determinative of a rate, said pulse generating means disposed within the master unit; c. plural selection means disposed within said master unit adapted independently to select pulses each at a given one of said frequencies each said selection means related to a chargeable activity; d. detection means associated with each of said selection means for detecting said pulses at the selected frequency; and e. individual register means associated with each of said detection means for counting the number of pulses detected by the respective detection means and continuously registering the monetary value chargeable to the related chargeable activity, and further wherein said detection means and said individual register means are incorporated in a plurality of accessory units, each accessory unit containing one selection means, one detection means, and one individual register, and wherein the master totalizing register continuously registers the sum total of the individual registers in each accessory unit.

Claim 3

A rate/time computer according to claim 1 wherein said pulse generating means comprises a circular disc having a plurality of holes therein, said disc being rotatable at a predetermined rate and a series of electrical switches connected in electrical circuits with feeler levers adapted to engage said holes whereby each switch provides a pulse of current in the connected electrical circuit as its respective feeler lever engages a hole.

Claim 4

A rate/time computer according to claim 2 wherein said plural selection means comprise a plurality of selection switches for completing an electrical path between a selected electrical switch of said pulse generating means and said detection means.

Claim 5

A rate/time computer according to claim 2 wherein said pulse of current is provided by the discharge of a capacitor. 5. A rate/time computer according to claim 1 wherein said detection means comprises single-throw switching contact, and a drive transistor, said contact adapted to connect said transistor across an electrical source responsive to a pulse from said pulse generating means and adapted to actuate the counters of said register means.

Claim 6

A rate/time computer as defined in claim 5 wherein said contact is also adapted to connect said drive transistor to a capacitor in a memory unit whereby said capacitor is charged in response to a pulse from said pulse generating means.

Claim 7

A rate/time computer as defined in claim 6 where said memory unit comprises a plurality of capacitors corresponding to each of said detecting means; means for providing a constant timed pulse which actuates in sequence switches associated with each of said capacitors adapted to discharge each of said capacitors, master totalizer counters associated with said capacitors, whereby each capacitor is tested in sequence and charged capacitors are discharged, actuating said master totalizers.

Claim 8

A rate/time computer for continuously registering monetary charges as a function of rate and time comprising: a. a master unit with a master totalizing register; b. pulse generating means adapted to provide electrical pulses at a plurality of frequencies, each frequency determinative of a rate, said pulse generating means disposed within the master unit; c. plural selection means in communication with said pulse generating means and adapted independently to select pulses each at a given one of said frequencies, each said selection means related to a chargeable activity; d. detection means in communication with each of said selection means for detecting the pulses of one or more of the selected frequencies; e. individual register means in communication with each of said detection means for counting the number of pulses detected and continuously registering the monetary value chargeable to the related chargeable activity; each individual register means including means to be individually or cumulatively responsive to one or more of the plurality of frequencies; f. a memory unit which comprises a plurality of capacitors corresponding to each of said detecting means; g. means for providing a constant timed pulse which actuates in sequence switches associated with each of said capacitors adapted to discharge each of said capacitors and master totalizer counters associated with said capacitors whereby each capacitor is tested in sequence and the charged capacitors are discharged actuating said master totalizers to provide a cumulative total of all detected pulses.

Claim 9

A rate/time computer for continuously registering monetary charges as a function of rate and time comprising: a. a master unit with a master totalizing register; b. pulse generating means adapted to provide electrical pulses at a plurality of frequencies, each frequency determinative of a rate, said pulse generating means disposed within the master unit; c. plural selection means in communication with said pulse generating means and adapted independently to select pulses each at a given one of said frequencies, each said selection means related to a chargeable activity; d. detection means in communication with each of said selection means for detecting the pulses of one or more of the selected frequencies; e. individual register means in communication with each of said detection means for counting the number of pulses detected and continuously registering the monetary value chargeable to the related chargeable activity; each individual register means including means to be individually or cumulatively responsive to one or more of the plurality of frequencies; f. a memory unit which comprises a plurality of capacitors corresponding to each of said detecting means; g. means for providing a constant timed pulse which actuates in sequence switches associated with each of said capacitors adapted to discharge each of said capacitors and master totalizer counters associated with said capacitors whereby each capacitor is tested in sequence and the charged capacitors are discharged actuating said master totalizers to provide a cumulative total of all detected pulses.