Circulating memory-refreshed display system

Claim 2

In combination: a source of timing pulses; a display system whose timing is independent of any signals stored in the circulating delay line memory set forth below connected to and operating synchronously with said source; a circulating delay line memory subject to drift coupled to said display system for delivering binary coded sequential signals a bit at a time representing the information to be displayed by said system, but which signals, because of drift of said memory, may not be in proper phase relationship with the operation of said display system; means controlled by said source of timing pulses receptive of said sequential signals from said memory for deriving therefrom signals in a desired phase relationship with the operation of said display system; and means receptive of said sequential signals for returning them a bit at a time to said circulating delay line memory in a predetermined fixed phase relationship with the operation of said display system.

Claim 3

In the combination set forth in claim 1, said display system comprising a television receiver.

Claim 4

In combination: a stable frequency source; a television receiver which derives its timing waveforms solely from said stable frequency source; a refresh delay line memory subject to drift for supplying a bit at a time the binary coded signals from which are derived the intensity modulation signals for creating and continuously refreshing the display of said television receiver; means controlled by said stable frequency source and receptive of the signals provided by said delay line memory for deriving therefrom signals which are synchronous with the timing waveforms of said television receiver; and means for returning to said delay line memory said synchronous signals a bit at a time such that they begin again to be supplied by said memory approximately one television field time later.

Claim 5

In combination: a stable frequency source; a television receiver which derives its timing waveforms solely from said stable frequency source; a refresh delay line memory subject to drift for supplying a bit at a time the binary coded signals from which are derived the intensity modulation signals for creating and continuously refreshing the display of said television receiver; means controlled by said stable frequency source and receptive of the signals provided by said delay line memory for deriving therefrom signals which are synchronous with the timing waveforms of said television receiver; and means for returning to said delay line memory said synchronous signals a bit at a time such that they begin again to be supplied by said memory approximately one television field time later.

Claim 6

In combination: n television receivers; a refresh delay line memory; means for storing in said delay line memory for each receiver p groups of signals, each group corresponding to m television lines, and also a blank space of a duration corresponding to at least the television vertical retrace period, where the p groups plus the blank space contain sufficient information for one television field but occupy not more than 1/nth of a television field time, and where the groups of signals for the respective receivers are stored in interlaced fashion so that the delay line memory supplies first a group of signals for one receiver then a group of signals for another receiver and so on; means responsive to each group of signals for translating said signals to intensity modulation signals which are synchronous with the timing of the corresponding television receiver and for applying them to said receiver; and means for returning each group of signals to said delay line memory at a time such that it is again produced by said delay line memory approximately one television field time later, where m, n and p are all integers greater than 1.

Claim 7

In combination: n television receivers; a refresh delay line memory; means for storing in said delay line memory for each receiver p groups of signals, each group corresponding to m television lines, and also a blank space of a duration corresponding to at least the television vertical retrace period, where the p groups plus the blank space contain sufficient information for one television field but occupy not more than 1/nth of a television field time, and where the groups of signals for the respective receivers are stored in interlaced fashion so that the delay line memory supplies first a group of signals for one receiver then a group of signals for another receiver and so on; means responsive to each group of signals for translating said signals to intensity modulation signals which are synchronous with the timing of the corresponding television receiver and for applying them to said receiver; and means for returning each group of signals to said delay line memory at a time such that it is again produced by said delay line memory approximately one television field time later, where m, n and p are all integers greater than 1.

Claim 8

In the combination set forth in claim 4, said refresh delay line memory having a delay equal to approximately one television field time.

Claim 9

In the combination set forth in claim 4, further including a stable frequency source connected to said n television receivers for synchronously controlling the operation of all of said receivers.

Claim 10

In combination: a stable frequency source; display means which derives its timing waveforms from said stable frequency source independently of the circulating memory set forth below and which has a screen on which an image created by successive fields are displayed; a circulating delay line memory subject to drift for supplying a bit at a time binary coded signals from which are derived the modulation signals for creating and continuously refreshing the image on the screen of said display means; means controlled by said stable frequency source and receptive of the signals provided by said circulating memory for deriving therefrom signals which are synchronous with the timing waveforms of said display means; and means for returning to said circulating delay line memory said synchronous signals a bit at a time, at a time such that they begin again to be supplied by said memory approximately one display means field time later.

Claim 11

In combination: a stable frequency source; display means which derives its timing waveforms from said stable frequency source independently of the circulating memory set forth below and which has a screen on which an image created by successive fields are displayed; a circulating delay line memory subject to drift for supplying a bit at a time binary coded signals from which are derived the modulation signals for creating and continuously refreshing the image on the screen of said display means; means controlled by said stable frequency source and receptive of the signals provided by said circulating memory for deriving therefrom signals which are synchronous with the timing waveforms of said display means; and means for returning to said circulating delay line memory said synchronous signals a bit at a time, at a time such that they begin again to be supplied by said memory approximately one display means field time later.

Claim 12

In combination: display means operating at a given rate; video generator means which accepts sequential input signals a bit at a time for a short interval at a rate substantially higher than said given rate and which converts them to video signals and supplies said video signals to said display means over an interval substantially longer than said short interval; refresh delay line memory means for supplying the sequential signals to be converted to video signals a bit at a time and at a rate substantially lower than that at which the video generator accepts signals; and means receptive of the signals supplied by said refresh memory means for supplying them a bit at a time to said video generator means at said substantially higher rate.

Claim 13

In combination: display means operating at a given rate; video generator means which accepts sequential input signals a bit at a time for a short interval at a rate substantially higher than said given rate and which converts them to video signals and supplies said video signals to said display means over an interval substantially longer than said short interval; refresh delay line memory means for supplying the sequential signals to be converted to video signals a bit at a time and at a rate substantially lower than that at which the video generator accepts signals; and means receptive of the signals supplied by said refresh memory means for supplying them a bit at a time to said video generator means at said substantially higher rate.

Claim 14

In the combination set forth in claim 8, said last-named means comprising a shift register, means for shifting said register at the operating rate of said refresh memory means during the interval said register receives signals therefrom, and means for shifting said register at said higher rate of said video generator means while supplying said signals to the latter.

Claim 15

In the combination set forth in claim 8, further including means for returning said signals supplied by said memory means to said memory means at the operating rate of said memory means.

Claim 16

In combination: display means operating at a given rate; video generator means which accepts input signals for a short interval at a rate substantially higher than said given rate and which converts them to video signals and supplies said video signals to said display means over an interval substantially longer than said given rate; refresh memory means for supplying the signals to be converted to video signals at a rate substantially lower than that at which the video generator accepts signals; shift register means receptive of the signals supplied by said refresh memory means for supplying them to said video generator means at said substantially higher rate; means for shifting said shift register means at the operating rate of said refresh memory means during the interval said shift register means receives signals therefrom, and means for shifting said shift register means at said higher rate of said video generator means while supplying said signals to the latter; and means for ring shifting said shift register means while applying its contents to said video generator to thereby retain said signals in said shift register means, and means for then opening said ring and shifting said signals out of said shift register means and back into said memory means at the operating rate of said memory means.

Claim 17

In combination: display means operating at a given rate; video generator means which accepts input signals for a short interval at a rate substantially higher than said given rate and which converts them to video signals and supplies said video signals to said display means over an interval substantially longer than said given rate; refresh memory means for supplying the signals to be converted to video signals at a rate substantially lower than that at which the video generator accepts signals; shift register means receptive of the signals supplied by said refresh memory means for supplying them to said video generator means at said substantially higher rate; means for shifting said shift register means at the operating rate of said refresh memory means during the interval said shift register means receives signals therefrom, and means for shifting said shift register means at said higher rate of said video generator means while supplying said signals to the latter; and means for ring shifting said shift register means while applying its contents to said video generator to thereby retain said signals in said shift register means, and means for then opening said ring and shifting said signals out of said shift register means and back into said memory means at the operating rate of said memory means.

Claim 18

In the combination set forth in claim 11, further including means for applying signals from said refresh memory means to said shift register means during the time the signals from said shift register means are being applied to said memory means.

Claim 19

The combination of: a delay line memory storing in coded form the fields for two television displays with signals for groups of scan lines for one display interlaced with signals for groups of scan lines for the other display; register means; means for loading said register means with the signals for one group of horizontal scan lines and for then ring shifting said signals once around said register within a period substantially shorter than that required to load said register mEans from said memory; video generator means receptive of said signals stored in said register means as they are being ring shifted for applying video signals to one display for a period substantially longer than that required to receive the corresponding coded signals from said delay line memory; and means for concurrently loading said register means with the signals for a group of scan lines for the other display while returning the signals stored in said register means to said delay line memory.

Claim 20

The combination of: a delay line memory storing in coded form the fields for two television displays with signals for groups of scan lines for one display interlaced with signals for groups of scan lines for the other display; register means; means for loading said register means with the signals for one group of horizontal scan lines and for then ring shifting said signals once around said register within a period substantially shorter than that required to load said register mEans from said memory; video generator means receptive of said signals stored in said register means as they are being ring shifted for applying video signals to one display for a period substantially longer than that required to receive the corresponding coded signals from said delay line memory; and means for concurrently loading said register means with the signals for a group of scan lines for the other display while returning the signals stored in said register means to said delay line memory.

Claim 21

The combination set forth in claim 13, wherein the delay line memory is subject to drift and further including: a stable frequency source; and means for synchronizing said signals produced by said delay line memory with said frequency source prior to loading them into said register means.

Claim 22

In combination: a television receiver for displaying two interlaced fields per frame; a delay line memory for storing coded signals for a single field for said receiver; translating means coupled to said delay line memory for translating said coded signals to video signals and for applying said video signals to said television receiver for effecting the display of one field of information on said receiver; and means for returning said coded signals to said delay line memory at a time such that they begin again to emerge from said memory in time for said translating means to produce the second field of a frame and to apply it to said receiver interlaced with said first field.

Claim 23

In combination: a television receiver for displaying two interlaced fields per frame; a delay line memory for storing coded signals for a single field for said receiver; translating means coupled to said delay line memory for translating said coded signals to video signals and for applying said video signals to said television receiver for effecting the display of one field of information on said receiver; and means for returning said coded signals to said delay line memory at a time such that they begin again to emerge from said memory in time for said translating means to produce the second field of a frame and to apply it to said receiver interlaced with said first field.

Claim 24

The combination set forth in claim 15, in which said delay line memory stores interlaced with said single field for said receiver, a second field of coded signals, this one for a second television receiver; a second television receiver; and a second translating mean and second means for returning, both as set forth in claim 15, for together deriving from said second field of coded signals two interlaced fields of a frame for said second television receiver.