US3598902A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gated differential gain control circuit for a television receiver
Assignee: Motorola Solutions Inc
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Filing: 1969-06-11
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Granted: 1971-08-10
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Expires: 1989-06-11
Abstract
Abstract A monolithic integrated automatic gain control system for a TV receiver includes a differential gating stage having one reference input, a gating pulse input and a synchronizing signal pulse input. This gating stage is responsive to simultaneous application of gating and sync pulses to provide an output signal proportional to the signal level of the video sync pulse. This output signal is supplied to a differential IF-AGC amplifier stage which supplies an amplified IF-AGC output signal to the IF amplifier of a TV receiver to control the gain thereof. A differential RF-AGC amplifier and delay stage is coupled to the IF-AGC amplifier stage output and provides a delayed RF-AGC signal which is supplied to the RF-amplifier of the TV receiver to provide a delayed RF gain control signal thereto.
Inventors
- 👤 Walter R Davis
- 👤 Gerald K Lunn
- 👤 James E Solomon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:25
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/52; H04N5/53
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
197 words
An automatic gain control circuit for a television receiver responsive to composite video signals including at least video sync pulses, the magnitude of which are subject to variation and further including means responsive to the sync pulses for producing gating pulses, the automatic gain control circuit including in combination: a reference transistor connected to a reference voltage terminal; a gating transistor differentially coupled to said reference transistor and adapted to receive said gating pulses for biasing said gating transistor to nonconduction and enabling said reference transistor to conduct; an input transistor differentially coupled to both said gating transistor and said reference transistor and adapted to receive said video sync pulses at the input thereof, said sync pulses operative to bias said input transistor to conduction when said video sync pulses override the reference potential on the reference voltage terminal at a time when gating pulses bias said gating transistor to nonconduction; means connected to an output electrode of at least one of said reference or input transistors for providing an output signal proportional to the signal level of said sync pulses; and means coupling said output signal to an amplifier for controlling the gain of the amplifier.
Claim 2
Dependent Claim
197 words
An automatic gain control circuit for a television receiver responsive to composite video signals including at least video sync pulses, the magnitude of which are subject to variation and further including means responsive to the sync pulses for producing gating pulses, the automatic gain control circuit including in combination: a reference transistor connected to a reference voltage terminal; a gating transistor differentially coupled to said reference transistor and adapted to receive said gating pulses for biasing said gating transistor to nonconduction and enabling said reference transistor to conduct; an input transistor differentially coupled to both said gating transistor and said reference transistor and adapted to receive said video sync pulses at the input thereof, said sync pulses operative to bias said input transistor to conduction when said video sync pulses override the reference potential on the reference voltage terminal at a time when gating pulses bias said gating transistor to nonconduction; means connected to an output electrode of at least one of said reference or input transistors for providing an output signal proportional to the signal level of said sync pulses; and means coupling said output signal to an amplifier for controlling the gain of the amplifier.
Claim 3
Dependent Claim
82 words
The automatic gain control circuit defined in claim 1 wherein said coupling means includes a delay stage having first and second differentially coupled transistors therein, said second transistor in said delay stage connected to a point of reference potential and said first transistor in said delay stage coupled to receive the output signal and conductively controlled thereby, one of said first and second transistors in said delay stage providing a delayed automatic gain control signal for controlling the gain of an amplifier.
Claim 4
Dependent Claim
101 words
The automatic gain control circuit defined in claim 2 wherein said delay stage further includes: a. a first emitter-follower buffer transistor coupled to the output of one of said first and second transistors in said delay stage for providing a desired level of output current, b. a lateral PNP transistor coupled to said first emitter follower buffer transistor for establishing a desired DC output voltage level for said delay stage, and c. a second emitter follower buffer transistor DC coupled to said lateral PNP transistor for providing a delayed automatic gain control output signal for controlling the gain of an amplifier.
Claim 5
Dependent Claim
93 words
The automatic gain control circuit defined in claim 1 wherein said coupling means includes an AGC amplifier stage including first and second differentially coupled transIstors therein, said second differentially coupled transistor in said AGC amplifier stage connected to point of reference potential and said first transistor in said AGC amplifier stage connected to receive said output signal and be conductively controlled thereby, one of said first and second transistors in said AGC amplifier stage providing a control output signal which is adapted to be coupled to an amplifier to control the gain thereof.
Claim 6
Dependent Claim
97 words
The automatic gain control circuit defined in claim 4 wherein said coupling means further includes a delay stage coupled to the output of said AGC amplifier stage and responsive to the control output signal thereof to provide a delayed automatic gain control signal, said delay stage responsive to predetermined, greater variations in the signal level of said sync pulse than said AGC amplifier stage to thereby provide a gain control signal which combines with the control output signal from said AGC amplifier to reduce the overall gain of the receiver with which said AGC circuit is used.
Claim 7
Dependent Claim
87 words
The automatic gain control circuit defined in claim 5 wherein said delay stage further includes: a. first and second differentially coupled transistors, said second differentially coupled transistor in said delay stage connected to a point of reference potential and said first differentially coupled transistor in said delay stage connected to receive an output signal from said AGC amplifier stage, and b. means for deriving a delayed automatic gain control signal from the output of one of said first and second differentially coupled transistors in said delay stage.
Claim 8
Dependent Claim
106 words
The automatic gain control circuit defined in claim 6, wherein said means for deriving a delayed automatic gain control signal includes: a. a first emitter-follower transistor connected to one of said first and second differentially coupled transistors in said delay stage for providing a desired current level in the output of said delay stage, b. a lateral PNP transistor connected to the output of said first emitter-follower transistor for establishing the DC level in the output of said delay stage, and c. a second, output emitter-follower transistor DC coupled to said lateral PNP transistor for providing a delayed automatic gain control signal at the output thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-09 | 1975-02-08 | 1975-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-09 | 1979-02-08 | 1979-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-09 | 1983-02-08 | 1983-08-10 | $7700.00 | Window Closed / Lapsed |