Line-determining circuit for pattern-indicating circuit

Claim 2

In a pattern-indicating circuit, a line-determining circuit for determining the continuity of lines of said pattern, said line-determining circuit comprising scanning means for scanning a pattern comprising a plurality of lines and producing scanning signals in accordance with said patterns; storage means connected to said scanning means for storing said scanning signals and for providing from said scanning signals line signals for lines of said pattern having specific slope components, said storage means comprising continuation means for determining the complete continuity and the noncontinuity of the specific slope components of the vertical lines of said pattern, the continuation means of said storage means comprising a first shift register having input and output means comprising a first shift register having input and output means and comprising a plurality of flip-flops, each having a set input, a reset input, a set output and a reset output, said storage means further comprising termination means for determining the complete termination and the nontermination of the specific slope components of the vertical lines of said pattern, said termination means comprising a plurality of flipflops, each having a set input, a reset input, a set output and a reset output, said storage means comprising a delay line and input means connecting said scanning means to the input means of said first shift register and connecting said scanning means to the input means of said second shift register via said delay line, a first plurality of AND gates each having an output, an input connected to the reset output of a corresponding flip-flop of said first shift register and another input connected tO the set output of the corresponding flip-flop of said second shift register, and a second plurality of AND gates each having an output, an input connected to the set output of a corresponding flip-flop of said first shift register and another input connected to the reset output of the corresponding flip-flop of said second shift register; continuation output means connected to the continuation means of said storage means for indicating said complete continuity and noncontinuity; and termination output means connected to the termination means of said storage means for indicating said complete termination and nontermination.

Claim 3

In a pattern-indicating circuit, a line-determining circuit for determining the continuity of lines of said pattern, said line-determining circuit comprising scanning means for scanning a pattern comprising a plurality of lines and producing scanning signals in accordance with said pattern; storage means connected to said scanning means for storing said scanning signals and for providing from said scanning signals line signals for lines of said pattern having specific slope components, said storage means comprising continuation means for determining the complete continuity and the noncontinuity of the specific slope components of the horizontal lines of said pattern, the continuation means of said storage means comprising a first shift register having input and output means and comprising a pair of flip-flops each having a set input, a reset input, a set output and a reset output, and a second shift register having input and output means and comprising a pair of flip-flops each having a set input, a reset input, a set output and a reset output, said storage means further comprising termination means for determining the complete termination and the nontermination of the specific slope components of the horizontal lines of said pattern, said termination means comprising said second shift register and a third shift register having input and output means and comprising a pair of flip-flops each having a set input, a reset input, a set output and a reset output, said storage means comprising a first delay line having a first delay time, a second delay line having a second delay time longer than the first delay time, and input means connecting said scanning means to input means of said first register, connecting said scanning means to the input means of said second shift register via said first delay line and connecting said scanning means to the input means of said third shift register via said second delay line, a first plurality of AND gates each having an output, an input connected to the set output of the first flip-flop of a corresponding one of said shift registers and another input connected to the reset output of the second flip-flop of the corresponding one of said shift registers, and a second plurality of AND gates each having an output, an input connected to the reset output of the first flip-flop of a corresponding one of said shift registers and another input connected to the set output of the second flip-flop of the corresponding one of said shift registers; continuation output means connected to the continuation means of said storage means for indicating said complete continuity and noncontinuity; and termination output means connected to the termination means of said storage means for indicating said complete termination and nontermination.

Claim 4

In a pattern-indicating circuit, a line-determining circuit for determining the continuity of lines of said pattern, said line-determining circuit comprising scanning means for scanning a pattern comprising a plurality of lines and producing scanning signals in accordance with said pattern; storage means connected to said scanning means for storing said scanning signals and for providing from said scanning signals line signals for lines of said pattern having specific slope components, said storage means comprising continuation means for determining the complete continuity and the noncontinuity of the specific slope components of the horizontal lines of said pattern, the continuation means of said storage means comprising a first shift register having input and output means and comprising a pair of flip-flops each having a set input, a reset input, a set output and a reset output, and a second shift register having input and output means and comprising a pair of flip-flops each having a set input, a reset input, a set output and a reset output, said storage means further comprising termination means for determining the complete termination and the nontermination of the specific slope components of the horizontal lines of said pattern, said termination means comprising said second shift register and a third shift register having input and output means and comprising a pair of flip-flops each having a set input, a reset input, a set output and a reset output, said storage means comprising a first delay line having a first delay time, a second delay line having a second delay time longer than the first delay time, and input means connecting said scanning means to input means of said first register, connecting said scanning means to the input means of said second shift register via said first delay line and connecting said scanning means to the input means of said third shift register via said second delay line, a first plurality of AND gates each having an output, an input connected to the set output of the first flip-flop of a corresponding one of said shift registers and another input connected to the reset output of the second flip-flop of the corresponding one of said shift registers, and a second plurality of AND gates each having an output, an input connected to the reset output of the first flip-flop of a corresponding one of said shift registers and another input connected to the set output of the second flip-flop of the corresponding one of said shift registers; continuation output means connected to the continuation means of said storage means for indicating said complete continuity and noncontinuity; and termination output means connected to the termination means of said storage means for indicating said complete termination and nontermination.

Claim 5

In a pattern-indicating circuit as claimed in claim 1, wherein said continuation output means comprises a flip-flop having a set input, a reset input, a set output and a reset output, and an AND gate having a plurality of inputs and an output connected to the reset input of said flip-flop, and wherein said storage means further comprises an AND gate having a plurality of inputs each connected to the output of a corresponding one of the first plurality of AND gates and an output connected to the set input of the flip-flop of said continuation output means and a plurality of inverters each connected between the output of a corresponding one of said first plurality of AND gates and a corresponding one of the inputs of the AND gate of said continuation output means whereby the flip-flop of said continuation output means is set when each of the AND gates of said first plurality of AND gates is in conductive condition and is reset when each of the AND gates of said first plurality of AND gates is in nonconductive condition thereby indicating the complete continuity and the noncontinuity of the specific slope components of the vertical lines of said pattern, and output means connected to the set output of the flip-flop of said continuation output means.

Claim 6

In a pattern-indicating circuit as claimed in claim 1, wherein said termination output means comprises a flip-flop having a set input, a reset input, a set output and a reset output and an AND gate having a plurality of inputs and an output connected to the set input of said flip-flop and wherein said storage means further comprises an AND gate having a plurality of inputs each connected to the output of a corresponding one of the second plurality of AND gates and an output connected to the reset input of the flip-flop of said termination output means and a plurality of inverters each connected between the output of a corresponding one of said second plurality of AND gates and a corresponding one of the inputs of the AND gate of said termination output means whereby the flip-flop of said termination output means is set when each of the AND gates of said second plurality of AND gates and a corresponding one of the inputs of the AND gate of said termination output means whereby flip-flop of said termination output means is set when each of the AND gates of said second plurality of AND gates is in conductive condition thereby indicating the complete termination and the nontermination of the specific slope components of the vertical lines of said pattern, and output means connected to the set output of the flip-flop of said termination output means.

Claim 7

In a pattern-indicating circuit as claimed in claim 1, wherein each of said first and second shift registers comprises three flip-flops.

Claim 8

In a pattern-indicating circuit as claimed in claim 1, wherein said delay line has a delay time equal to one scanning period of said scanning means.

Claim 9

In a pattern-indicating circuit as claimed in claim 2, wherein said continuation output means comprises a circulating-type delay line having a delay time equal to one scanning period, an input and an output, first and second AND gates each having a pair of inputs and an output and an OR gate having a pair of inputs each connected to the output of a corresponding one of the first and second AND gates and an output connected to the input of said circulating-type delay line, the output of said circulating-type delay line being connected to an input of said first AND gate, and wherein said storage means further comprises a first AND gate having a plurality of inputs each connected to the output of a corresponding one of the first plurality of AND gates and an output connected to an input of the second AND gate of said continuation output means, a second AND gate having a plurality of inputs and an output, a plurality of inverters each connected between the output of a corresponding one of said first plurality of AND gates and a corresponding corresponding input of said second AND gate and an inverter connected between the output of said second AND gate and the other input of the first AND gate of said continuation output means, means for supplying scanning signals to the other input of the second AND gate of said continuation output means, and output means connected to the output of said circulating type delay line.

Claim 10

In a pattern-indicating circuit as claimed in claim 2, wherein said termination output means comprises a circulating-type delay line having a delay time equal to one scanning period, an input aNd an output, first and second AND gates each having a pair of inputs and an output and an OR gate having a pair of inputs each connected to the output of a corresponding one of the first and second AND gates and an output connected to the input of said circulating-type delay line, the output of said circulating-type delay line being connected to an input of said first AND gate, and wherein said storage means further comprises a first AND gate having a plurality of inputs each connected to the output of a corresponding one of the second plurality of AND gates and an output connected to an input of the second AND gate of said termination output means, a second AND gate having a plurality of inputs and an output, a plurality of inverters each connected between the output of a corresponding one of said second plurality of AND gates and a corresponding input of said second AND gate and an inverter connected between the output of said second AND gate and the other input of the first AND gate of said termination output means, means for supplying scanning signals to the other input of the second AND gate of said termination output means, and output means connected to the output of said circulating-type delay line.

Claim 11

In a pattern-indicating circuit as claimed in claim 2, wherein said first delay line has a delay time equal to one scanning period of said scanning means and said second delay line has a delay time equal to two scanning periods of said scanning means.