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US3597662A Expired / Lapsed US ⏱️ 0.0 years remaining

Off delay solid-state time delay apparatus

Assignee: Westinghouse Electric Corp
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Filing: 1968-05-28
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Granted: 1971-08-03
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Expires: 1988-05-28
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Abstract

Abstract An off delay circuit utilizes an output controlled rectifier together with diodes and transistors and an RC network to provide time delay. The controlled rectifier is maintained in conduction by a controllable half cycle trigger current and a half cycle phase shifted load current.

Inventors

  • 👤 Wardell Gary

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 16:45
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/35; H03K17/00; H03K17/28; H03K17/292; H03K17/51; H03K17/56; H03K17/72; H03K17/725

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 726 words
Off delay time delay apparatus comprising, in combination, first and second teRminals adapted to be connected to a singlephase alternating current line, first and second lead means connected to the first and second terminals respectively, a full wave rectifier having one input directly connected to the second lead means and having the other input thereof adapted to be connected by way of a relay coil to the first lead means, a controlled rectifier having a control element and having the anode-cathode path thereof connected across the output of the full wave rectifier, circuit means connecting the controlled rectifier anode to the positive output lead of the full wave rectifier and connecting the controlled rectifier cathode to the negative output lead of the controlled rectifier, the controlled rectifier while gated on forming a closed alternating current switch and causing full energizing current to flow from the alternating current line through the relay coil, said controlled rectifier being normally in a nonconductive condition, other circuit means including in series a first diode, a first resistor and a first Zener diode connecting the control element of the controlled rectifier to the first lead means, a second resistor connecting the control element of the controlled rectifier to the negative output lead of the full wave rectifier, a pair of complementary NPN and PNP transistors, the emitter of the NPN transistor being connected to the negative terminal of the full wave rectifier, means forming a connection between the collector of the NPN transistor and the base of the PNP transistor, an R-C timing circuit including a timing capacitor and an adjustable timing resistor connected in parallel, one terminal of the parallel timing circuit being connected to the base of the PNP transistor and the other terminal of the parallel R-C timing circuit being connected to said aforementioned negative output lead of the full wave rectifier, a second diode connecting the emitter of the PNP transistor to the junction between the first resistor and the first Zener diode, current flowing through said second diode and through the emitter-base junction of the PNP transistor producing a voltage across the base thereof determined by the voltage drop in the timing resistor, said last-named voltage causing the pair of complementary transistors to conduct whereby the voltage at the junction between the first resistor and the first Zener diode is reduced to a value less than the Zener voltage of said first Zener diode and no gate current is supplied through said first Zener diode to the control element of the controlled rectifier, an initiating switch having one terminal thereof connected to the first lead and to the first terminal, circuit means including in series a third resistor, a third diode and a fourth diode connecting the other terminal of the initiating switch to the timing capacitor, a second Zener diode connected between the junction between the third and fourth diodes and said negative output lead of the full wave rectifier, closing the initiating switch causing the aforementioned timing capacitor to be quickly charged to a voltage which when applied to the base of the PNP transistor renders the pair of complementary transistors nonconductive thereby causing current to cease to flow through the first diode connected between the emitter of the PNP transistor and the junction between the first resistor and the first Zener diode, thereby causing the voltage at said junction to rise to a value which exceeds the Zener voltage of the first Zener diode thereby causing a gating current to pass through the first Zener diode and to be applied to the control element of the controlled rectifier causing said controlled rectifier to be gated on and causing full current to flow through said relay coil, said initiating switch being adapted to be thereafter opened, said timing resistor discharging said timing capacitor within a predetermined time interval after the switch is opened to a voltage at which current begins to flow through The emitter-base junction of the PNP transistor and through the second diode connected to the junction between the first resistor and the first Zener diode thereby causing the voltage at said junction to fall to a value less than the Zener voltage of the first Zener diode thereby causing the controlled rectifier to assume a nonconductive circuit open condition and thereby causing current through the relay coil to fall to zero.
Claim 2
Dependent Claim 726 words
Off delay time delay apparatus comprising, in combination, first and second teRminals adapted to be connected to a singlephase alternating current line, first and second lead means connected to the first and second terminals respectively, a full wave rectifier having one input directly connected to the second lead means and having the other input thereof adapted to be connected by way of a relay coil to the first lead means, a controlled rectifier having a control element and having the anode-cathode path thereof connected across the output of the full wave rectifier, circuit means connecting the controlled rectifier anode to the positive output lead of the full wave rectifier and connecting the controlled rectifier cathode to the negative output lead of the controlled rectifier, the controlled rectifier while gated on forming a closed alternating current switch and causing full energizing current to flow from the alternating current line through the relay coil, said controlled rectifier being normally in a nonconductive condition, other circuit means including in series a first diode, a first resistor and a first Zener diode connecting the control element of the controlled rectifier to the first lead means, a second resistor connecting the control element of the controlled rectifier to the negative output lead of the full wave rectifier, a pair of complementary NPN and PNP transistors, the emitter of the NPN transistor being connected to the negative terminal of the full wave rectifier, means forming a connection between the collector of the NPN transistor and the base of the PNP transistor, an R-C timing circuit including a timing capacitor and an adjustable timing resistor connected in parallel, one terminal of the parallel timing circuit being connected to the base of the PNP transistor and the other terminal of the parallel R-C timing circuit being connected to said aforementioned negative output lead of the full wave rectifier, a second diode connecting the emitter of the PNP transistor to the junction between the first resistor and the first Zener diode, current flowing through said second diode and through the emitter-base junction of the PNP transistor producing a voltage across the base thereof determined by the voltage drop in the timing resistor, said last-named voltage causing the pair of complementary transistors to conduct whereby the voltage at the junction between the first resistor and the first Zener diode is reduced to a value less than the Zener voltage of said first Zener diode and no gate current is supplied through said first Zener diode to the control element of the controlled rectifier, an initiating switch having one terminal thereof connected to the first lead and to the first terminal, circuit means including in series a third resistor, a third diode and a fourth diode connecting the other terminal of the initiating switch to the timing capacitor, a second Zener diode connected between the junction between the third and fourth diodes and said negative output lead of the full wave rectifier, closing the initiating switch causing the aforementioned timing capacitor to be quickly charged to a voltage which when applied to the base of the PNP transistor renders the pair of complementary transistors nonconductive thereby causing current to cease to flow through the first diode connected between the emitter of the PNP transistor and the junction between the first resistor and the first Zener diode, thereby causing the voltage at said junction to rise to a value which exceeds the Zener voltage of the first Zener diode thereby causing a gating current to pass through the first Zener diode and to be applied to the control element of the controlled rectifier causing said controlled rectifier to be gated on and causing full current to flow through said relay coil, said initiating switch being adapted to be thereafter opened, said timing resistor discharging said timing capacitor within a predetermined time interval after the switch is opened to a voltage at which current begins to flow through The emitter-base junction of the PNP transistor and through the second diode connected to the junction between the first resistor and the first Zener diode thereby causing the voltage at said junction to fall to a value less than the Zener voltage of the first Zener diode thereby causing the controlled rectifier to assume a nonconductive circuit open condition and thereby causing current through the relay coil to fall to zero.
Claim 3
Dependent Claim 40 words
Off delay time delay apparatus according to claim 1 in which the pair of complementary transistors are additionally described as providing a high gain thereby permitting the R-C timing circuit to utilize a capacitor charged to a relatively low voltage.
Claim 4
Dependent Claim 34 words
Off delay time delay apparatus according to claim 2 in which the high gain of the complementary pair of transistors permits increasing the resistance value of the timing resistor thereby increasing the timing range.
Claim 5
Dependent Claim 69 words
Off delay time delay apparatus according to claim 1 in which the gating signal applied to the control element of the controlled rectifier by way of the first diode, first resistor and first Zener diode has a time phase difference from the alternating current in the relay coil thereby assisting in maintaining the controlled rectifier in a conductive condition and thereby reducing the power dissipation in the controlled rectifier.
Claim 6
Dependent Claim 36 words
Off delay time delay apparatus according to claim 1 including in addition a further Zener diode connected across the anode-cathode terminals of the controlled rectifier to protect the controlled rectifier from transient peak voltages applied thereacross.
Claim 7
Dependent Claim 107 words
Off delay time delay apparatus according to claim 1 in which the relay coil current is conducted through the controlled rectifier as a pulsating direct current, and including in addition resistance means connecting the controlled rectifier to the first terminal whereby the full cycle of the alternating waveform between the first and second terminals flows through the resistance means, said resistance means being operatively connected to the controlled rectifier whereby the half wave current through the resistance means flows through the controlled rectifier, said half wave current through the resistance means being substantially 90 electrical degrees out of phase with the alternating current through the relay coil.
Claim 8
Dependent Claim 55 words
Off delay time delay apparatus according to claim 1 in which said fourth diode interposed between the timing capacitor and the voltage regulating second Zener diode isolates the timing capacitor from the last-named Zener diode voltage regulator when the timing period starts thereby insuring that said timing capacitor can discharge only through said timing resistor.
Claim 9
Dependent Claim 56 words
Off delay time delay apparatus according to claim 1 including in addition a further resistor and a further capacitor connected in series with each other and in shunt with the anode-cathode path through the controlled rectifier comprising a dv/dt slowdown circuit to thereby prevent premature firing of the controlled rectifier with a fast rising anode voltage.
Claim 10
Dependent Claim 52 words
Off delay time delay apparatus according to claim 1 including a further capacitor connected from the base of the PNP transistor to the junction between the first resistor and the first Zener diode, said last-named capacitor providing means for reducing the high frequency noise voltage sensitivity of said complementary pair of transistors.
Claim 11
Dependent Claim 189 words
In off delay time delay apparatus of the type having a pair of terminals adapted to be connected to an alternating current line and including a full wave rectifier having one input thereof connected to one of said terminals, the other input of the full wave rectifier being adapted to be connected by a relay coil to the other of said terminals, and a controlled rectifier having the anode-cathode path thereof connected across the output of the full wave rectifier with transistor circuit means including Zener diode means for initiating conduction in the controlled rectifiEr, the improvement which includes means for maintaining the controlled rectifier in conduction without a direct current supply therefor and without retriggering the controlled rectifier each half cycle, said means including resistor means connected to one of the terminals and to the cathode of the controlled rectifier for obtaining a half wave pulsating direct current substantially 90* different in phase from the pulsating direct current flowing through said controlled rectifier as a result of alternating current flowing through said relay coil, and causing the current through the resistor means to flow through the controlled rectifier.
Claim 12
Dependent Claim 189 words
In off delay time delay apparatus of the type having a pair of terminals adapted to be connected to an alternating current line and including a full wave rectifier having one input thereof connected to one of said terminals, the other input of the full wave rectifier being adapted to be connected by a relay coil to the other of said terminals, and a controlled rectifier having the anode-cathode path thereof connected across the output of the full wave rectifier with transistor circuit means including Zener diode means for initiating conduction in the controlled rectifiEr, the improvement which includes means for maintaining the controlled rectifier in conduction without a direct current supply therefor and without retriggering the controlled rectifier each half cycle, said means including resistor means connected to one of the terminals and to the cathode of the controlled rectifier for obtaining a half wave pulsating direct current substantially 90* different in phase from the pulsating direct current flowing through said controlled rectifier as a result of alternating current flowing through said relay coil, and causing the current through the resistor means to flow through the controlled rectifier.
Claim 13
Dependent Claim 238 words
In off delay time delay apparatus of the type having a pair of input terminals adapted to be connected to an alternating current line with a full wave rectifier having one input thereof connected to one of said terminals and having the other input thereof adapted to be connected by way of a relay coil to the other of said terminals, and having a controlled rectifier connected with the anode-cathode path thereof across the output of the full wave rectifier to provide an alternating current switch which while the controlled rectifier is conductive causes full alternating current to flow through the relay coil, the improvement which comprises trigger means including a Zener diode and a resistor in series therewith with the junction between the Zener diode and the resistor connected to the control element of the controlled rectifier, diode means and other resistor means connecting the Zener diode to one of said terminals, normally conductive means connected to the Zener diode for maintaining the voltage drop across the Zener diode at a value less than the Zener voltage thereof whereby no gating current is supplied to the controlled rectifier, and means including an initiating switch and circuit means connected thereto for rendering said normally conductive means nonconductive to thereby cause the voltage across the Zener diode to rise to a value sufficient to cause current to flow therethrough and thereby supply a gate signal to the controlled rectifier.
Claim 14
Dependent Claim 238 words
In off delay time delay apparatus of the type having a pair of input terminals adapted to be connected to an alternating current line with a full wave rectifier having one input thereof connected to one of said terminals and having the other input thereof adapted to be connected by way of a relay coil to the other of said terminals, and having a controlled rectifier connected with the anode-cathode path thereof across the output of the full wave rectifier to provide an alternating current switch which while the controlled rectifier is conductive causes full alternating current to flow through the relay coil, the improvement which comprises trigger means including a Zener diode and a resistor in series therewith with the junction between the Zener diode and the resistor connected to the control element of the controlled rectifier, diode means and other resistor means connecting the Zener diode to one of said terminals, normally conductive means connected to the Zener diode for maintaining the voltage drop across the Zener diode at a value less than the Zener voltage thereof whereby no gating current is supplied to the controlled rectifier, and means including an initiating switch and circuit means connected thereto for rendering said normally conductive means nonconductive to thereby cause the voltage across the Zener diode to rise to a value sufficient to cause current to flow therethrough and thereby supply a gate signal to the controlled rectifier.

References Cited (Backward Citations)

US3210605A Cited
US3131318A Cited
US3320493A Cited
US3355632A Cited
US3478250A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-08-02 1975-02-01 1975-08-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-08-02 1979-02-01 1979-08-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-08-02 1983-02-01 1983-08-03 $7700.00 Window Closed / Lapsed

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