US3596259A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay stem of sampled signals using a circulating memory
Assignee: KDDI Corp
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Filing: 1968-12-17
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Granted: 1971-07-27
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Expires: 1988-12-17
Abstract
Abstract A system for delaying sampled signals including a circulating memory having a delay circuit in which the delay time unit is designed Td; a sampling circuit for producing a sampling pulse train having a period Ts, wherein Td and Ts are each equal to an integer-multiple of the duration of the sampled signal circulating in the circulating memory, and the delay time unit Td is not equal to an integer-multiple of the sampling period Ts; a read-right circuit for entering and withdrawing sampled pulses to and from the memory; an output circuit for receiving signals readout of the memory; and a control timing circuit for generating pulses to operate these various circuits. The sampled signals which are delayed by the circulating memory are derived from the circulating memory at least at predetermined times at each of which an integer-multiple of the delay time unit Ts and an integer-multiple of the sampled period Ts coincide with each other. The sampled signals delayed may be derived from the circulating memory at each of the predetermined times only, or at plural times a predetermined period from one of the predetermined times and the just succeeding one of the predetermined times.
Inventors
- 👤 Hiroichi Teramura
- 👤 Naohiko Hattori
- 👤 Sumitoshi Ando
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:49
CPC Classifications
G; G11; G11C; G11C21/00; H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026; H03K5/1504; H03K5/159
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
241 words
A system for delaying sampled signals obtained by sampling the signal of at least one input channel by use of at least one sampling pulse train, comprising: sampling circuit means for sampling an information signal, said sampling circuit means including means for generating sampling pulses having a period Ts therebetween and having a predetermined sampling duration for each period Ts; a circulating memory for storing said sampled information signal, said circulating memory having an input terminal and an output terminal, and having delay means connected between said input and output terminals; output circuit means for generating delayed information signals; write-read circuit means having a write circuit means connected to said sampling circuit means and said input terminal of said memory, and having read circuit means connected to said output terminal of said memory and to said output circuit means; control circuit means for generating timing signals, said control circuit means being connected to said sampling circuit means, said write-read circuit means, and said output circuit means for causing said time period Ts and said sampling duration time to have relationships with said time period Td, wherein Ts NOT = n Td, where n is an integer, and wherein each Ts and Td is a different integermultiple of said sampling duration time; and means connected to said output circuit means for triggering said output circuit means to generate said delayed information signals at least at predetermined times when Td and Ts coincide.
Claim 2
Independent Claim
241 words
A system for delaying sampled signals obtained by sampling the signal of at least one input channel by use of at least one sampling pulse train, comprising: sampling circuit means for sampling an information signal, said sampling circuit means including means for generating sampling pulses having a period Ts therebetween and having a predetermined sampling duration for each period Ts; a circulating memory for storing said sampled information signal, said circulating memory having an input terminal and an output terminal, and having delay means connected between said input and output terminals; output circuit means for generating delayed information signals; write-read circuit means having a write circuit means connected to said sampling circuit means and said input terminal of said memory, and having read circuit means connected to said output terminal of said memory and to said output circuit means; control circuit means for generating timing signals, said control circuit means being connected to said sampling circuit means, said write-read circuit means, and said output circuit means for causing said time period Ts and said sampling duration time to have relationships with said time period Td, wherein Ts NOT = n Td, where n is an integer, and wherein each Ts and Td is a different integermultiple of said sampling duration time; and means connected to said output circuit means for triggering said output circuit means to generate said delayed information signals at least at predetermined times when Td and Ts coincide.
Claim 3
Dependent Claim
37 words
A delay system according to claim 1, in which said means connected to said output circuit means comprises means for triggering said output circuit means to generate said delayed signals at each of the predetermined times only.
Claim 4
Dependent Claim
75 words
A delay system according to claim 1, in which said means connected to said output circuit means comprises means for triggering said output circuit means to generate said delayed signals at plural times during a predetermined period from one of the predetermined times and the just succeeding one of the predetermined times, whereby the same memory space allocated in the circulating memory are used to delay a plurality of sampled signals in the predetermined period.
Claim 5
Dependent Claim
30 words
A delay system according to claim 3, in which the predetermined period is equal to the least common multiple of the delay time unit Td and the sampling period Ts.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-26 | 1975-01-25 | 1975-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-26 | 1979-01-25 | 1979-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-26 | 1983-01-25 | 1983-07-27 | $7700.00 | Window Closed / Lapsed |