US3596160A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlocking directional control and braking circuit for brushless dc motor
Assignee: Litton Marine Systems Inc
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Filing: 1969-10-01
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Granted: 1971-07-27
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Expires: 1989-10-01
Abstract
Abstract A control circuit for a reversible brushless DC motor (BDCM) includes first and second channels to supply clockwise and counterclockwise command signals to the motor in response to corresponding directional input signals. The two channels are interlocked so that a command signal in one channel disables the other channel. Each channel also includes means to delay the formation of a command signal for a predetermined time and a braking circuit coupled to each channel for providing a braking signal in the absence of a command signal.
Inventors
- 👤 Rodney G Rakes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:01
CPC Classifications
H; H02; H02P; H02P6/00; H02P6/06; H02P6/24; H02P6/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
210 words
A control circuit for a reversible BDCM comprising individual channels for supplying clockwise and counterclockwise command signals to an external BDCM in response to clockwise and counterclockwise input signals respectively, delay means in each channel for delaying the formation of a command signal for a specific time after the reception of a corresponding input signal, switching means in each channel, said delay means including a resistor and a capacitor connected in series with the switching means in the same channel, said delay means being constructed so that the magnitude of the command signal is a function of the charge on said capacitor, said switching means being constructed and arranged to turn on in response to an input signal received by the channel, said delay means being actuated when the switching means in the same channel is turned on, means to disable the switching means in one channel while the switching means in the opposite Channel is turned on, said disabling means further including means to maintain the switching means in said one channel in a disabled condition for a specified time after the switching means in the opposite channel is turned off, and braking means for supplying a braking signal to said BDCM in the absence of a command signal.
Claim 2
Dependent Claim
210 words
A control circuit for a reversible BDCM comprising individual channels for supplying clockwise and counterclockwise command signals to an external BDCM in response to clockwise and counterclockwise input signals respectively, delay means in each channel for delaying the formation of a command signal for a specific time after the reception of a corresponding input signal, switching means in each channel, said delay means including a resistor and a capacitor connected in series with the switching means in the same channel, said delay means being constructed so that the magnitude of the command signal is a function of the charge on said capacitor, said switching means being constructed and arranged to turn on in response to an input signal received by the channel, said delay means being actuated when the switching means in the same channel is turned on, means to disable the switching means in one channel while the switching means in the opposite Channel is turned on, said disabling means further including means to maintain the switching means in said one channel in a disabled condition for a specified time after the switching means in the opposite channel is turned off, and braking means for supplying a braking signal to said BDCM in the absence of a command signal.
Claim 3
Dependent Claim
37 words
The apparatus of claim 1 wherein said resistor and capacitor are proportioned to provide a capacitor charging rate such that the command signal reaches a specific level only after the expiration of a predetermined capacitor charging time.
Claim 4
Dependent Claim
44 words
The apparatus of claim 2 wherein each switching means includes an output transistor having a pair of output terminals and wherein the corresponding delay means, braking means, and disabling means are all actuated from the same one of said pair of transistor output terminals.
Claim 5
Dependent Claim
41 words
The apparatus of claim 3 wherein each disabling means includes a shorting transistor connected across the input to the switching means in the same channel, said shorting transistor being further connected to respond to the switching circuit in the opposite channel.
Claim 6
Dependent Claim
47 words
The apparatus of claim 4 further including first and second power busses for connecting said control circuit to a source of power, said apparatus also including first rectifying means for coupling the other of said pair of transistor output terminals directly to one of said power busses.
Claim 7
Dependent Claim
77 words
The apparatus of claim 5 wherein the resistor in each of said delay means is connected directly to the transistor output terminal and the capacitor in the same delay means is connected directly to the other of said power busses, each of said delay means further including a first diode connected serially between said resistor and said capacitor, said apparatus further characterized in that command signals are taken from the junction of said resistor and said diode.
Claim 8
Dependent Claim
34 words
The apparatus of claim 6 wherein said disabling means is further coupled to said capacitor through a second diode, said second diode being oriented to pass current from said capacitor to said disabling means.
Claim 9
Dependent Claim
52 words
The apparatus of claim 7 wherein said braking means includes a braking resistance-capacitance network coupled between the other of said power busses and the output terminal on both of said output transistors, said braking network having a time constant that is short with respect to that of said command signal delay means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-26 | 1975-01-25 | 1975-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-26 | 1979-01-25 | 1979-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-26 | 1983-01-25 | 1983-07-27 | $7700.00 | Window Closed / Lapsed |