Fet logic gate circuits

Claim 2

A gate circuit, which comprises: means for providing a signal on a first lead; means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead; means for transferring the signal on the first lead to a first output port in response to a second data signal of one type, and for transferring the signal on the third lead to the first output port in response to a second data signal of a second type; means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead; an output load impedance; and means for transferring the signAl at the first output port to the output load impedance in response to a third data signal of one type, and for transferring the signal on the fourth lead to the output load impedance in response to a third data signal of a second-type.

Claim 3

A gate circuit, as recited in claim 1, where the output load impedance is a capacitor.

Claim 4

A gate circuit, comprising: means for providing a first data signal on a first lead and an inversion thereof on a second lead; means for providing a first constant voltage on a third lead and a second and different constant voltage on a fourth lead; first and second field effect transistors each having a gate and a first and second controlled terminals; means for connecting the first field effect transistor to the first and third leads, the first controlled terminal being connected to the third lead and the gate being connected to the first lead, the second controlled terminal serving as a first output port; means for connecting the second field effect transistor to the second and fourth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the second lead; and means for connecting the second controlled terminal of the first field effect transistor to the second controlled terminal of the second field effect transistor.

Claim 5

A gate circuit, comprising: means for providing a first data signal on a first lead and an inversion thereof on a second lead; means for providing a first constant voltage on a third lead and a second and different constant voltage on a fourth lead; first and second field effect transistors each having a gate and a first and second controlled terminals; means for connecting the first field effect transistor to the first and third leads, the first controlled terminal being connected to the third lead and the gate being connected to the first lead, the second controlled terminal serving as a first output port; means for connecting the second field effect transistor to the second and fourth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the second lead; and means for connecting the second controlled terminal of the first field effect transistor to the second controlled terminal of the second field effect transistor.

Claim 6

A gate as recited in claim 3, further comprising: means for providing a second data signal on a fifth lead and an inversion thereof on a sixth lead; third and fourth field effect transistors each having a gate and first and second controlled terminals; means for connecting the third field effect transistor to the first output port and to the sixth lead, the first controlled terminal being connecting to the first output port and the gate being connected to the sixth lead, the second controlled terminal serving as a second output port; means for connecting the fourth field effect transistor to the third and fifth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the fifth lead; and means for connecting the second controlled terminal of the third field effect transistor to the second controlled terminal of the fourth field effect transistor.

Claim 7

A circuit as recited in claim 4, wherein the means for providing a first data signal on a first lead and an inversion of said first data signal on a second lead comprises a first phase splitting circuit, and wherein the means for providing a second data signal on a fifth lead and an inversion of the second data signal on a sixth lead comprises a second phase splitting circuit.

Claim 8

A gate circuit, comprising: means for providing a first data signal on a first lead; means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead; means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead; first, second, third and fourth field effect transistors each having a gate and first and second controlled terminals; means for connecting the first field effect transistor to the first and third leads, the first controlled terminal being connected to the first lead and the gate being connected to the third lead, the second controlled terminal forming a first output port; means for connecting the second field effect transistor to the second and third leads, the first controlled terminal being connected to the third lead and the gate being connected to the second lead; means for connecting the third field effect transistor to the fourth and fifth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the fifth lead, the second controlled terminal providing a second output port; means for connecting the gate of the fourth field effect transistor to the fourth lead; means for interconnecting the second contrOlled terminals of the first, second and fourth field effect transistors; and means for connecting the first controlled terminal of the fourth field effect transistor to the second controlled terminal of the third field effect transistor.

Claim 9

A gate circuit, comprising: means for providing a first data signal on a first lead; means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead; means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead; first, second, third and fourth field effect transistors each having a gate and first and second controlled terminals; means for connecting the first field effect transistor to the first and third leads, the first controlled terminal being connected to the first lead and the gate being connected to the third lead, the second controlled terminal forming a first output port; means for connecting the second field effect transistor to the second and third leads, the first controlled terminal being connected to the third lead and the gate being connected to the second lead; means for connecting the third field effect transistor to the fourth and fifth leads, the first controlled terminal being connected to the fourth lead and the gate being connected to the fifth lead, the second controlled terminal providing a second output port; means for connecting the gate of the fourth field effect transistor to the fourth lead; means for interconnecting the second contrOlled terminals of the first, second and fourth field effect transistors; and means for connecting the first controlled terminal of the fourth field effect transistor to the second controlled terminal of the third field effect transistor.

Claim 10

A gate circuit as recited in claim 6 wherein the means responsive to a second data signal for providing the second data signal on a second lead and an inversion thereof on a third lead comprises a first phase splitting circuit and wherein the means responsive to a third data signal for providing the third data signal on a fourth lead and an inversion thereof on a fifth lead comprises a second phase splitting circuit.

Claim 11

A MOSFET coincidence gate circuit for producing an output signal to charge a capacitor only in response to one selected combination of a plurality of binary data signals, and for discharging the capacitor, if previously charged, for all other combinations of the data signals, which comprises: means for providing two input signals for each bit, one corresponding to the bit and one to its complement; a plurality of logic-steering FETs (''''LFs'''') arranged in a sequence, each of which has its gate connected to a first one of the input signals for an associated bit selected such that each LF becomes conductive only when the associated bit assumes the selected state; means for supplying a capacitor-charging signal to a first controlled terminal of a first LF in the sequence, each subsequent LF having its first controlled terminal connected in series with the second controlled terminal of preceding LF, the output capacitor being connected to the second controlled terminal of the last LF in the sequence so that the capacitor is connected to the charging signal only whenever all of the LFs have been rendered conductive in response to the selected combination of the input signals; and a plurality of ground-return FETs (''''GFs'''') arranged in a sequence corresponding to that of the LFs, each of which has its gate connected to the second input signal for an associated bit such that each GF becomes conductive only when the associated bit assumes the nonselected state, the last GF in the sequence having its controlled terminals connected in series between the capacitor and a source of ground potential to provide a ground-discharge path for the capacitor whenever the last bit assumes the nonselected state, each preceding GF being connected in series between the first controlled terminal of the following LF and a source of ground potential to provide a ground-discharge path for the capacitor whenever the associated bit assumes the nonselected state and all following bits have assumed the selected state.

Claim 12

A MOSFET coincidence gate circuit for producing an output signal to charge a capacitor only in response to one selected combination of a plurality of binary data signals, and for discharging the capacitor, if previously charged, for all other combinations of the data signals, which comprises: means for providing two input signals for each bit, one corresponding to the bit and one to its complement; a plurality of logic-steering FETs (''''LFs'''') arranged in a sequence, each of which has its gate connected to a first one of the input signals for an associated bit selected such that each LF becomes conductive only when the associated bit assumes the selected state; means for supplying a capacitor-charging signal to a first controlled terminal of a first LF in the sequence, each subsequent LF having its first controlled terminal connected in series with the second controlled terminal of preceding LF, the output capacitor being connected to the second controlled terminal of the last LF in the sequence so that the capacitor is connected to the charging signal only whenever all of the LFs have been rendered conductive in response to the selected combination of the input signals; and a plurality of ground-return FETs (''''GFs'''') arranged in a sequence corresponding to that of the LFs, each of which has its gate connected to the second input signal for an associated bit such that each GF becomes conductive only when the associated bit assumes the nonselected state, the last GF in the sequence having its controlled terminals connected in series between the capacitor and a source of ground potential to provide a ground-discharge path for the capacitor whenever the last bit assumes the nonselected state, each preceding GF being connected in series between the first controlled terminal of the following LF and a source of ground potential to provide a ground-discharge path for the capacitor whenever the associated bit assumes the nonselected state and all following bits have assumed the selected state.

Claim 13

A gate circuit as recited in claim 8, wherein: an additional binary data signal is provided, the state of which is to be detected in combination with the others, the two possible states of the additional data signal being capable of (1) charging and (2) discharging the capacitor as recited in claim 8, the reverse being true of the complement of the additional data signal; and the means for supplying the capacitor-charging signal comprises means for connecting a selected one of the additional data signal and its complement to the first controlled terminal of the first LF, the one being selected to charge the capacitor when the additional data signal assumes the selected state, and to provide a ground-discharge path for the capacitor whenever the additional bit assumes the nonselected state and all bits recited in claim 8 have assumed the selected state.

Claim 14

A gate circuit as recited in claim 8, wherein: the states of the binary data signals are (1) a discrete potential capable of rendering the FETs conductive and (2) a ground potential not so capable; the second data input signal in each case comprises the discrete potential when the associated bit assumes the nonselected state to render each GF conductive in that case; and the source of grouNd potential to which a controlled terminal of each GF is connected comprises the first data input signal associated with that GF, which is a ground potential whenever that GF is conductive.