US3596072A
Expired / Lapsed
US
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Error-detecting circuitry in adder system
Assignee: Hitachi Ltd
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Filing: 1969-05-23
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Granted: 1971-07-27
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Expires: 1989-05-23
Abstract
Abstract Three signals representing augend and addend are supplied to a carry save adder and a predicted carry circuit which generates a predicted carry signal for each order when corresponding bits of said three signals are coincident. An error check signal is generated by an error check circuit which checks parity of sum and carry signals produced by said carry save adder and said predicted carry signal. By employing the predicted carry circuit, the number of circuit components for the error detection is greatly reduced, and hence the cost of the error detection is reduced correspondingly.
Inventors
- 👤 Shoji Iwamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:18
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/509; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
82 words
An adder system including error-detecting circuitry comprising a carry save adder, the operation error of which is to be detected, means for generating a predicted carry signal for conserving the parity of sum and carry signals from input signals of said carry save adder representing an augend and addend, and means for detecting said operation error by checking the parity of signals representing sum and carry as a result of the operation of said carry save adder and said predicted carry signal.
Claim 2
Dependent Claim
82 words
An adder system including error-detecting circuitry comprising a carry save adder, the operation error of which is to be detected, means for generating a predicted carry signal for conserving the parity of sum and carry signals from input signals of said carry save adder representing an augend and addend, and means for detecting said operation error by checking the parity of signals representing sum and carry as a result of the operation of said carry save adder and said predicted carry signal.
Claim 3
Dependent Claim
43 words
An adder system according to claim 1, wherein said predicted carry signal generating means comprises a predicted carry circuit for generating such a predicted carry signal as making the parity of said predicted carry signal, said sum signal, and said carry signal constant.
Claim 4
Dependent Claim
64 words
An adder system according to claim 2, wherein said predicted carry circuit comprises a plurality of unit predicted carry circuits each provided correspondingly to each order of said carry save adder for generating a predicted carry signal for the corresponding order when two signals representing an augend of the corresponding order and a signal representing an addend of the corresponding order are not coincident.
Claim 5
Dependent Claim
66 words
An adder system according to claim 2, wherein said predicted carry circuit comprises a plurality of unit predicted carry circuits each provided correspondingly to each order of said carry save adder for generating a predicted carry signal for the corresponding order when two signals representing an augend of the corresponding order and a signal representing an addend of the corresponding order are coincident with each other.
Claim 6
Dependent Claim
83 words
An adder system according to claim 1, wherein said detecting means comprises a plurality of parity check circuit for checking the parity of said sum signal and carry signal for each bit generated by said carry save adder and said predicted carry signal for each bit generated by said signal-generating means, and a check circuit for generating an error check signal when at least one of said parity check circuits generates a signal indicating that the last-mentioned parity is not a predetermined one.
Claim 7
Dependent Claim
86 words
An adder system according to claim 3, wherein said check circuit comprises AND circuits for forming the logical product of output signals from said parity check circuits, and said signal generating means comprises a plurality of unit predicted carry circuits each provided correspondingly to each order of said carry save adder for generating a predicted carry signal for the corresponding order when two signals representing an augend of the corresponding order and a signal representing an addend of the corresponding order are coincident with each other.
Claim 8
Dependent Claim
83 words
An adder system according to claim 3, wherein said check circuit comprises OR circuits for forming the logical sum of output signals from said parity check circuits, and said signal-generating means comprises a plurality of unit predicted carry circuits each provided correspondingly to each order of said carry save adder for generating a prEdicted carry signal for the corresponding order when two signals representing an augend of the corresponding order and a signal representing an addend of the corresponding order are not coincident.
Claim 9
Dependent Claim
104 words
An adder system including error-detecting circuitry comprising a carry save adder, the operation error of which is to be detected, means for generating a predicted carry signal for conserving the parity of carry and sum signals from input signals of said carry save adder representing an augend and addend, parity generating means for generating parity bit signals at each appropriate number of bits of a sum signal and carry signal produced by said carry save adder and of said predicted carry signal, respectively, and means for detecting said operation error by checking the parity of said parity bit signals produced by said parity-generating means.
Claim 10
Dependent Claim
104 words
An adder system including error-detecting circuitry comprising a carry save adder, the operation error of which is to be detected, means for generating a predicted carry signal for conserving the parity of carry and sum signals from input signals of said carry save adder representing an augend and addend, parity generating means for generating parity bit signals at each appropriate number of bits of a sum signal and carry signal produced by said carry save adder and of said predicted carry signal, respectively, and means for detecting said operation error by checking the parity of said parity bit signals produced by said parity-generating means.
Claim 11
Dependent Claim
43 words
An adder system according to claim 8, wherein said predicted carry signal generating means comprises a predicted carry circuit for generating such a predicted carry signal as making the parity of said predicted carry signal, said sum signal, and said carry signal constant.
Claim 12
Dependent Claim
64 words
An adder system according to claim 9, wherein said predicted carry circuit comprises a plurality of unit predicted carry circuits each provided correspondingly to each order of said carry save adder for generating a predicted carry signal for the corresponding order when two signals representing an augend of the corresponding order and a signal representing an addend of the corresponding order are not coincident.
Claim 13
Dependent Claim
66 words
An adder system according to claim 9, wherein said predicted carry circuit comprises a plurality of unit predicted carry circuits each provided correspondingly to each order of said carry save adder for generating a predicted carry signal for the corresponding order when two signals representing an augend of the corresponding order and a signal representing an addend of the corresponding order are coincident with each other.
Claim 14
Dependent Claim
46 words
An adder system according to claim 8, wherein said parity-generating means comprises three parity generators provided correspondingly to said sum signal, carry signal and predicted carry signal for generating said parity bit signals by checking the parity at each appropriate number of bits of these signals.
Claim 15
Dependent Claim
61 words
An adder system according to claim 10, wherein said detecting means comprises at least one parity check circuit for checking the parity of corresponding bits of said parity bit signals generated by said three parity generators, and a check circuit for generating an error check signal when a signal generated by said parity check circuit is not of a predetermined parity.
Claim 16
Dependent Claim
37 words
An adder system according to claim 10, wherein said parity generator corresponding to said sum signal comprises parity check circuits for generating the parity of corresponding bits of parity signals being transmitted accompanying said augend and addend.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-26 | 1975-01-25 | 1975-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-26 | 1979-01-25 | 1979-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-26 | 1983-01-25 | 1983-07-27 | $7700.00 | Window Closed / Lapsed |