Method of manufacturing a semiconductor device comprising complementary transistors
Abstract
Abstract A METHOD OF MAKING AN INTEGRATED CIRCUIT CONTAINING NPN AND COMPLEMENTARY PNP TRANSISTORS IS DESCRIBED. IN A PREFERRED ARRANGEMENT, A P SUBSTRATE WITHOUT ACTIVE BURIED LAYERS IS COVERED WITH A FIRST N EPITAXIAL LAYER IN WHICH AN N+ BURIED LAYER FOR THE NPN TRANSISTOR AND A P+ BURIED LAYER FOR THE PNP TRANSISTOR IS PROVIDED. THEN A SECOND N EPITAXIAL LAYER IS PROVIDED. THE N EMITTER AND P BASE ARE PROVIDED BY DIFFUSION OVER THE P+ BURIED LAYER, OUT THE N BASE IS CONSTITUTED BY THE SECOND EPITAXIAL LAYER. THE P COLLECTOR IS FORMED BY THE BURIED LAYER, TO WHICH A DIFFUSED CONTACT IS MADE. THE TWO BURIED LAYERS REMAIN SPACED FROM THE SUBSTRATE AND THE SURFACE. THUS, THE PNP TRANSISTOR IS ISOLATED BY THE FIRST EPITAXIAL LAYER.
Inventors
- 👤 Michel De Brebisson
- 👤 Jean-Claude Frouin
- 👤 Jacques Thire
Bibliographic Details
Claims Analysis
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