General purpose digital computer

Claim 2

In a general purpose, stored program computer the combination comprising: a random access memory configuration having a first portion which includes a first plurality of individually addressable storage locations for storing information signals in representation of a plurality of different and independent computing programs, including a first and a second program, each program of the plurality including operands and instructions for execution of each of the programs, said memory configuration havIng a second portion which includes a second plurality of individually addressable storage locations for storing information signals and having access speed faster than the speed for access to the locations of the first plurality, a location of the second plurality being individually addressable by a block selector code and an in-block code; memory access control means for receiving memory addressing signals and providing access to the locations of the first plurality to withdraw the content of and/or load the same or a new content into the accessed location; program means including the memory access control means and operating to withdraw instruction signals from the memory in representation of the program that is currently being executed, the program means including first means to provide instruction addresses to the memory access control in sequence of the current program as defined by a sequence of instructions, the program means including means for receiving signals representing the individual instructions as withdrawn, the second means for receiving instruction signals having a plurality of sections of different operative significance and including first, second and third sections and a section for holding an operate code of an instruction signal, at least some of the instruction signals as received by the second means including, for each instruction, two in-block codes set, respectively, into the first and second sections, and an operand addressing code set into the third section for serving as operand memory addressing signal for the memory access control means; processor means responsive to the operate code held in the operate code section of the second means to provide instruction execution operations including operations for at least some of the instructions that can be executed requiring operands held in locations in either or both portions of the memory and including operations which for some of the instructions require participation of an accumulator, and/or of general purpose registers such as source and/or destination registers for information signals further including third means defining the operating state of the processor means as executing a particular program; a block selector register holding a block selector code and providing a block selector signal in dependence thereon and connected to said second portion of the memory for rendering a block of the second plurality storage locations available for use as general purpose registers, accumulators and index registers to the exclusion of the remaining locations of the second plurality not included in the block as selected by the current block selector code held in said block selector register; fourth means connected to be responsive to the in-block code in the first section of the second means to access a location of the selected block, there being means in processor means operating to combine the content of the latter location in the selected block with the operand addressing code held in the third section of the second means and providing an indexed operand address as addressing signals to said memory access control means for at least some of the instructions in the program; fifths means connected to be responsive to the in-block code held as content in the second section in the second means to access a location in the selected block and being operative for at least some instructions of the program, the accessed location to serve as accumulator or general purpose register, the fifth means operating during operation of the access control means and in response to the operand address as derived from the same instruction that included the in-block code; and supervisory means including the processor means and operating pursuant to execution of instructions not pertaining to the first and second program, to change operation of the program means from executing the first program of the plurality to the second program of the plurality independently from completion of the firSt program, the processor including sixth means collecting the content of the first means, of the third means, and of the block selector register as defining the state of the first program at the time of the change to the second program and storing said contents into particular ones of the locations of the first plurality, and including seventh means to withdraw the content of second particular ones of the locations of the first plurality to provide a new instruction address to the first means pertaining the second program, a new state content for the third means and a new block selector code signal to the block selector register, thereby rendering a different block of second plurality memory locations available as accumulator, index register and general register.

Claim 3

The combination as in claim 1, the supervisory means including an additional program for determining and varying the particular ones of the locations of the first plurality as to their association with the first and second program.

Claim 4

In a computer as set forth in claim 1, the memory locations of the first plurality being grouped in pages addressable by a page code, each page having a similar plurality of locations, addressable by an in-page code, a memory location of the first plurality being addressable by concurrence of a page code and an in-page code; the memory access control means including a map which includes a plurality of registers, each holding signals in representation of a particular memory page code, the access control means further including: means (a) connected to be responsive to the memory addressing signals received by the access control means and separating first and second portions in each addressing signal received; means (b) connected to be responsive to the first portion of the separated addressing signals, and addressing a register of the plurality; means (c) connected to be responsive to the page code held in the accessed register to access the corresponding memory page; and means (d) connected to access a memory location of the first plurality, within the accessed page and in response to said separated second portion as in-page addressing code.

Claim 5

The combination as set forth in claim 3, the third means including a first representation as to utilization of the map, there being means to control accessing of a memory page directly in response to the first representation by operation of and as directly represented by the first portion of an addressing signal, the third means when providing a second representation providing for control of directly accessing a register of the plurality, the said representation in the third means being changed by operation of the sixth and seventh means upon a change from executing the first program to execution of the second program.

Claim 6

In a computer as set forth in claim 3, including a plurality storage means respectively associated with the registers of the plurality of the map for holding codes representing access restrictions to the memory page defined by the content of the respectively associated register of the plurality.

Claim 7

The combination as in claim 1 including a third program stored in the memory and executed, the third program having relatively low priority, including a first and a second interrupt channel accessing directly first and second memory locations of the first plurality, respectively, upon receiving interrupt signals; an interrupt in the first channel initiating execution of an instruction held in the first memory location, and causing the sixth means to collect the content of the first and third means and of the block selector register defining the state of the third program to be stored into first particular ones of the memory locations associated with the first program; an interrupt in the second channel initiating execution of an instruction in the second memory location causing the sixth means to collect the content of the first and third Means and of the block selector register defining the state of the third or first program depending on the time of occurrence of the interrupt in the second interrupt channel, and to place the collected content into second particular ones of the memory locations of the first plurality associated with the second program and independently from which program was interrupted by the interrupt in the second interrupt channel, the seventh means operating in response to instructions in the first and second memory locations to place the program means and the selector register under control of the first or second program.

Claim 8

The combination as in claim 1 the supervisory means including a plurality of interrupt channels, connected respectively to directly access one of a plurality of particular memory locations of the first plurality and respectively dedicated to the interrupt channels, the interrupt channels interconnected to obtain a priority chain of response so that only one channel at a time can access the respectively associated particular memory location, at least some of the particular memory locations holding particular instructions; the sixth means of the processor means responding particularly to the particular instruction.

Claim 9

The combination as in claim 7, the supervisory means including means (a) included in the processor and operating in response to at least one further particular instruction to provide a time metering operation, the latter instruction held in a further particular memory location of the first plurality, there being an additional interrupt channel receiving timing signals, causing direct accessing of the further particular memory location to place the processor under control of the means (a) to execute the further particular instruction in between execution of two instructions of the first program; and means (b) operating in response to metering of a particular period of time after repeated execution of the further particular instruction to provide an interrupt signal to one interrupt channel of the plurality.

Claim 10

In a general purpose, stored program computer the combination comprising: a random access memory configuration having a first portion which includes a first plurality of individually addressable storage locations for storing information signals in representation of a plurality of different and independent computing programs, including a first and a second program, each program of the plurality including operands and instructions for execution of each of the programs, said memory configuration having a second portion which includes a second plurality of individually addressable storage locations for storing information signals and having access speed faster than the speed for access to the locations of the first plurality, a location of the second plurality being individually addressable by a block selector code and an in-block code: Memory access control means for receiving memory addressing signals and providing access to the locations of the first plurality to withdraw the content of and/or load the same or a new content into the accessed location; program means including the memory access control means and operating to withdraw instruction signals from the memory in representation of the program that is currently being executed, the program means including first means to provide instruction addresses to the memory access control in sequence of the program as defined by a sequence of instruction and being currently executed, the program means including second means for receiving signals representing the individual instructions as withdrawn, the second means for receiving instruction signals having a plurality of sections of different operative significance and including first and second and third sections and a section for holding an operate code of an instruction signal, at least some of the instruction signals as received by the second means including, for each instruction, two in-Block codes set into the first and second section, and an operand addressing code set into the third section for serving as operand memory addressing signal for the memory access control means; processor means responsive to the operate code held in the operate code section of the second means to provide instruction execution operations including operands held in locations in either or both portions of the memory and including operations which for some of the instructions that can be executed require participation of an accumulator, and/or of general purpose registers such as source and/or destination registers for information signals further including third means defining the operating state of the processor means as executing a particular program; a block selector register holding a block selector code and providing a block selector signal in dependence thereon and connected to said second portion of the memory for rendering a block of the second plurality storage locations available as index registers general purpose registers and accumulators to the exclusion of the remaining locations of the second plurality not included in the block as selected by the current block selector register; fourth means connected to be responsive to the two in-block codes held as content in the first and second sections in the second means to sequentially access locations in the selected block and being operative for at least some instructions of the program, the location accessed first holding an indexing number the fourth means including address modification means to change the content of the third section before becoming effective as memory address, the subsequently accessed location in the selected block to serve as accumulator or general purpose register; fifth means including a plurality of interrupt channels including a first and a second channel connected to directly access, respectively, a first or second particular memory location of the first plurality upon receiving an interrupt signal, the fifth means further including circuit means interconnecting the interrupt channels to obtain a priority chain of response to interrupt signals, the first channel having higher priority than the second channel; sixth means included in the processor to be responsive to a particular instruction, for collecting program state signals representing the content of the first and third means and the current block selector code and placing the signals in memory locations of the first plurality designated by the particular instruction; seventh means operating subsequently to the sixth means, for withdrawing new program state signals representing a new content for the first and third means, and a new block selector code, from memory locations also designated by the particular instruction to obtain a change in program; there being a first and a second one of the particular instruction stored, respectively, in the first and second particular memory locations differing in the addressing of the designated locations, interruption of a program that is currently executed, by an interrupt signal in the first or in the second channel causes the signals of the interrupted program as collected by operation of the sixth means to be stored in different designated locations as identified by the respective instruction as taken from the first or second particular memory location, and different program state signals representing different new contents for the first and third means and the block selection register are withdrawn from correspondingly different designated locations to commence execution of the first or a second program; an interrupt signal in the first channel subsequent to an interrupt signal in the second channel causing the sixth means to store the program state signals representing the current state of the second program to be stored in the memory locations designated by the instruction in the first particular location.

Claim 11

In a general purpose, stored program computer the combination comprising: a random access memory configuration having a first portion which includes a first plurality of individually addressable storage locations for storing information signals in representation of a plurality of different and independent computing programs, including a first and a second program, each program of the plurality including operands and instructions for execution of each of the programs, said memory configuration having a second portion which includes a second plurality of individually addressable storage locations for storing information signals and having access speed faster than the speed for access to the locations of the first plurality, a location of the second plurality being individually addressable by a block selector code and an in-block code: Memory access control means for receiving memory addressing signals and providing access to the locations of the first plurality to withdraw the content of and/or load the same or a new content into the accessed location; program means including the memory access control means and operating to withdraw instruction signals from the memory in representation of the program that is currently being executed, the program means including first means to provide instruction addresses to the memory access control in sequence of the program as defined by a sequence of instruction and being currently executed, the program means including second means for receiving signals representing the individual instructions as withdrawn, the second means for receiving instruction signals having a plurality of sections of different operative significance and including first and second and third sections and a section for holding an operate code of an instruction signal, at least some of the instruction signals as received by the second means including, for each instruction, two in-Block codes set into the first and second section, and an operand addressing code set into the third section for serving as operand memory addressing signal for the memory access control means; processor means responsive to the operate code held in the operate code section of the second means to provide instruction execution operations including operands held in locations in either or both portions of the memory and including operations which for some of the instructions that can be executed require participation of an accumulator, and/or of general purpose registers such as source and/or destination registers for information signals further including third means defining the operating state of the processor means as executing a particular program; a block selector register holding a block selector code and providing a block selector signal in dependence thereon and connected to said second portion of the memory for rendering a block of the second plurality storage locations available as index registers general purpose registers and accumulators to the exclusion of the remaining locations of the second plurality not included in the block as selected by the current block selector register; fourth means connected to be responsive to the two in-block codes held as content in the first and second sections in the second means to sequentially access locations in the selected block and being operative for at least some instructions of the program, the location accessed first holding an indexing number the fourth means including address modification means to change the content of the third section before becoming effective as memory address, the subsequently accessed location in the selected block to serve as accumulator or general purpose register; fifth means including a plurality of interrupt channels including a first and a second channel connected to directly access, respectively, a first or second particular memory location of the first plurality upon receiving an interrupt signal, the fifth means further including circuit means interconnecting the interrupt channels to obtain a priority chain of response to interrupt signals, the first channel having higher priority than the second channel; sixth means included in the processor to be responsive to a particular instruction, for collecting program state signals representing the content of the first and third means and the current block selector code and placing the signals in memory locations of the first plurality designated by the particular instruction; seventh means operating subsequently to the sixth means, for withdrawing new program state signals representing a new content for the first and third means, and a new block selector code, from memory locations also designated by the particular instruction to obtain a change in program; there being a first and a second one of the particular instruction stored, respectively, in the first and second particular memory locations differing in the addressing of the designated locations, interruption of a program that is currently executed, by an interrupt signal in the first or in the second channel causes the signals of the interrupted program as collected by operation of the sixth means to be stored in different designated locations as identified by the respective instruction as taken from the first or second particular memory location, and different program state signals representing different new contents for the first and third means and the block selection register are withdrawn from correspondingly different designated locations to commence execution of the first or a second program; an interrupt signal in the first channel subsequent to an interrupt signal in the second channel causing the sixth means to store the program state signals representing the current state of the second program to be stored in the memory locations designated by the instruction in the first particular location.

Claim 12

The combination as set forth in claim 9, each interrupt channel of the plurality having a programmable program status, determining its relative priority among the interrupt channels of the plurality the processor including means operating in response to a particular instruction having a particular operate code to change the relative priority status of the individual ones of the interrupt channels of the plurality, as determined by the circuit means.

Claim 13

The combination as set forth in claim 9, including means to store an interrupt signal in the second channel if occurring after an interrupt signal in the first channel caused the computer to shift to the first program, to defer the execution of the second program until completion of the first program, but prior to resumption of the initial program when having lower priority than the second program.

Claim 14

The combination as in claim 9, including another particular instruction, included in the first and second program operative at the respective conclusion thereof causing the seventh means to take the program state signals of the second program out of the locations in which they were placed by operation of the seventh means when the second program was interrupted by the interrupt signal in the first channel and to place those status signals into the first and third means and into the selector code register, for resumption of the second program, the other particular instruction when operative at the conclusion of the second program causing analogously resumption of execution of the initial program.

Claim 15

The combination as in claim 9, including timing means operating to establish particular points in time of acceptance of an interrupt signal, the timing means including means (a) establishing such points in time at the conclusion of execution of each instruction; means (b) establishing such points in time at the conclusion of particular phases within execution of same instruction; and means (c) establishing such points in time a predetermined period after the respective previous point in time.

Claim 16

In a general purpose, stored program computer the combination comprising: a random access memory configuration having a first portion which includes a first plurality of individually addressable storage locations for storing information signals in representation of a plurality of different and independent computing programs including a first and a second program, each program of the plurality including operands and instructions for execution of each of the programs, said memory configuration having a second portion which includes a second plurality of individually addressable storage locations for storing information signals and having access speed faster than the speed for access to the locations of the first plurality; memory access control means for receiving memory addressing signals and providing access to the locations of the first plurality to withdraw the content of and/or load the same or a new content into the accessed location; program means including the memory access control means and operating to withdraw instruction signals from the memory in representation of the program that is currently being executed, the program means including first means to provide instruction addresses to the memory access control in sequence of the current program as defined by a sequence of instruction, the program means including second means for receiving signals representing the individual instructions as withdrawn, the second means for receiving instruction signals having a plurality of sections of different operative significance and including first and second sections and a section for holding an operate code of an instruction signal, at least some of the instruction signals as received by the second means including, for each instruction a second-plurality-addressing code set into the first section, and an operand addressing code set into the second section for serving as operand memory addressing signal for the mEmory access control means; processor means responsive to the operate code held in the operate code section of the second means to provide instruction execution operations including operands held in locations in either or both portions of the memory and including operations which for some of the instructions that can be executed require participation of an accumulator, and/or of general purpose resistors such as source and/or destination registers for information signals, further including third means defining the operating state of the processor means as executing a particular program; fourth means connected to be responsive to the code held as content in the first section in the second means to access a location of the second plurality and being operative for at least some instructions of the program, the accessed location to serve as accumulator or general register; fifths means including a plurality of interrupt channels including a first and a second channel connected to directly access, respectively, a first or second particular memory location of the first plurality, respectively in response to reception of interrupt demand signals, an interrupt demand signal in the first or in the second channel having caused access to the first or second particular memory location thereby initiates execution of the respective instruction held in the respective particular memory location to obtain turnover of the processor and program means to the first or to the second program; circuit means of interconnecting the interrupt channels to obtain a priority chain of response to interrupt signals, the first channel having higher priority than the second channel; sixth means included in the processor to be responsive to a particular instruction for collecting program status signals representing the content of the first and third means and placing the signals in memory locations of the first plurality designated by the particular instruction; seventh means operating subsequently to the sixth means for withdrawing new program status signals representing a new content for the first and third means, from memory locations also designated by the particular instruction to obtain a change in program; there being a first and a second one of the particular instruction stored, respectively, in the first and second particular memory locations differing in the addressing of the designated locations, interruption of a current program by an interrupt signal in the first or second channel causes the program status signals of the interrupted program as collected by operation of the sixth means to be stored in different designated locations, and different program status signals representing different new contents for the first and second means are withdrawn from correspondingly different designated locations to commence execution of the first or the second program; and means included in the processor and operating in response to second particular ones of the instructions to change the priority state of the interrupt channels of the plurality, permitting the first and second channels to reverse priority.

Claim 17

In a general purpose, stored program computer the combination comprising: a random access memory configuration having a first portion which includes a first plurality of individually addressable storage locations for storing information signals in representation of a plurality of different and independent computing programs including a first and a second program, each program of the plurality including operands and instructions for execution of each of the programs, said memory configuration having a second portion which includes a second plurality of individually addressable storage locations for storing information signals and having access speed faster than the speed for access to the locations of the first plurality; memory access control means for receiving memory addressing signals and providing access to the locations of the first plurality to withdraw the content of and/or load the same or a new content into the accessed location; program means including the memory access control means and operating to withdraw instruction signals from the memory in representation of the program that is currently being executed, the program means including first means to provide instruction addresses to the memory access control in sequence of the current program as defined by a sequence of instruction, the program means including second means for receiving signals representing the individual instructions as withdrawn, the second means for receiving instruction signals having a plurality of sections of different operative significance and including first and second sections and a section for holding an operate code of an instruction signal, at least some of the instruction signals as received by the second means including, for each instruction a second-plurality-addressing code set into the first section, and an operand addressing code set into the second section for serving as operand memory addressing signal for the mEmory access control means; processor means responsive to the operate code held in the operate code section of the second means to provide instruction execution operations including operands held in locations in either or both portions of the memory and including operations which for some of the instructions that can be executed require participation of an accumulator, and/or of general purpose resistors such as source and/or destination registers for information signals, further including third means defining the operating state of the processor means as executing a particular program; fourth means connected to be responsive to the code held as content in the first section in the second means to access a location of the second plurality and being operative for at least some instructions of the program, the accessed location to serve as accumulator or general register; fifths means including a plurality of interrupt channels including a first and a second channel connected to directly access, respectively, a first or second particular memory location of the first plurality, respectively in response to reception of interrupt demand signals, an interrupt demand signal in the first or in the second channel having caused access to the first or second particular memory location thereby initiates execution of the respective instruction held in the respective particular memory location to obtain turnover of the processor and program means to the first or to the second program; circuit means of interconnecting the interrupt channels to obtain a priority chain of response to interrupt signals, the first channel having higher priority than the second channel; sixth means included in the processor to be responsive to a particular instruction for collecting program status signals representing the content of the first and third means and placing the signals in memory locations of the first plurality designated by the particular instruction; seventh means operating subsequently to the sixth means for withdrawing new program status signals representing a new content for the first and third means, from memory locations also designated by the particular instruction to obtain a change in program; there being a first and a second one of the particular instruction stored, respectively, in the first and second particular memory locations differing in the addressing of the designated locations, interruption of a current program by an interrupt signal in the first or second channel causes the program status signals of the interrupted program as collected by operation of the sixth means to be stored in different designated locations, and different program status signals representing different new contents for the first and second means are withdrawn from correspondingly different designated locations to commence execution of the first or the second program; and means included in the processor and operating in response to second particular ones of the instructions to change the priority state of the interrupt channels of the plurality, permitting the first and second channels to reverse priority.

Claim 18

The combination as in claim 14, each interrupt channel of the plurality including means (a) for storing an interrupt demand signal received, until no other interrupt channel of respective higher priority requests control over the program means and processor means; and means (b) connected to be responsive to execution of a particular one of the second particular instructions further inhibiting or permitting accessing of the particular memory locations accessed directly upon reception or storage by the means (a) of an interrupt demand signal when no interrupt channel of respective higher priority has control over processor and program means.

Claim 19

In a general purpose computer as set forth in claim 14 the interrupt channels of the plurality including a particular channel of relatively high priority responsive to clocking signals for updating and testing a number held in the memory location associated with the particular interrupt channel; and means responsive to a particular resulting number of said updated number to provide an interrupt signal to a said second interrupt channel included in the plurality and having relatively low priority, the second interrupt channel being said enable channel causing accessing of said even plurality of memory locations.

Claim 20

In a general purpose computer, the combination comprising: a memory having a plurality of individually addressable storage locations for storing manifestations of instructions and operands, the memory being subdivided into pages and each storage location being identified and addressable by a page address and an in-page address, the instructions including an operate code, some of the instructions including a memory addressing code and a register code for selecting a register; a plurality of interrupt channels, each for receiving an interrupt demand signal, the channels being interconnected to establish an order of priority of response of the several channels, a channel when transmitting an interrupt demand signal being enabled for transmission only when respective channels of higher priority have not received an interrupt demand signal; access control means for providing addressing signals to the memory for accessing a storage location of the memory in accordance with the addressing signal as provided, and including a program counter for causing the sequential providing of addressing signals for accessing storage locations holding instructions, and including means individually responsive to transmitted interrupt demand signals for accessing particular storage locations in the memory respectively and individually associated with said interrupt channels; a plurality of individually addressable memory registers, divided into blocks, all registers pertaining to a block being addressable by a register code as provided in an instruction, the register of a block being addressable independently from each other; a block pointer register for holding a manifestation of the current, exchangeable pointer code and connected to the memory registers for operatively preparing a block of said memory registers for individual addressing via the register code for use as general register and accumulator, a change in pointer code changes the block as so prepared; mapping means responsive to said addressing signals and including a plurality of registers individually addressable by the page address portion of said addressing signals, the registers of the mapping means respectively holding a changeable substitute page address for changing the page address as included in an addressing signal provided by the control means, in accordance with a programmable pattern; a plurality of control elements for controlling the utilization of said mapping means and for providing access restriction to said memory locations; and means responsive to the operate code of an instruction withdrawn from memory in response to an interrupt demand signal transmitted through an enabled interrupt channel of the plurality, for operating the access control means for sequentially accessing an even plurality of memory locations, and including means (a) for recording in the first half of the latter plurality signals of the plurality of control elements, the current block pointer code and the content of the program counter, and means (b) for reading state signals, a code and a number from the second half of the latter plurality and means (c) for causing the state signals as read to be set into the said control elements, the code to be set into the pointer register, and the number to be set into the program counter.

Claim 21

In a general purpose computer, the combination comprising: a memory having a plurality of individually addressable storage locations for storing manifestations of instructions and operands, the memory being subdivided into pages and each storage location being identified and addressable by a page address and an in-page address, the instructions including an operate code, some of the instructions including a memory addressing code and a register code for selecting a register; a plurality of interrupt channels, each for receiving an interrupt demand signal, the channels being interconnected to establish an order of priority of response of the several channels, a channel when transmitting an interrupt demand signal being enabled for transmission only when respective channels of higher priority have not received an interrupt demand signal; access control means for providing addressing signals to the memory for accessing a storage location of the memory in accordance with the addressing signal as provided, and including a program counter for causing the sequential providing of addressing signals for accessing storage locations holding instructions, and including means individually responsive to transmitted interrupt demand signals for accessing particular storage locations in the memory respectively and individually associated with said interrupt channels; a plurality of individually addressable memory registers, divided into blocks, all registers pertaining to a block being addressable by a register code as provided in an instruction, the register of a block being addressable independently from each other; a block pointer register for holding a manifestation of the current, exchangeable pointer code and connected to the memory registers for operatively preparing a block of said memory registers for individual addressing via the register code for use as general register and accumulator, a change in pointer code changes the block as so prepared; mapping means responsive to said addressing signals and including a plurality of registers individually addressable by the page address portion of said addressing signals, the registers of the mapping means respectively holding a changeable substitute page address for changing the page address as included in an addressing signal provided by the control means, in accordance with a programmable pattern; a plurality of control elements for controlling the utilization of said mapping means and for providing access restriction to said memory locations; and means responsive to the operate code of an instruction withdrawn from memory in response to an interrupt demand signal transmitted through an enabled interrupt channel of the plurality, for operating the access control means for sequentially accessing an even plurality of memory locations, and including means (a) for recording in the first half of the latter plurality signals of the plurality of control elements, the current block pointer code and the content of the program counter, and means (b) for reading state signals, a code and a number from the second half of the latter plurality and means (c) for causing the state signals as read to be set into the said control elements, the code to be set into the pointer register, and the number to be set into the program counter.

Claim 22

In a digital computer for processing stored and external information signals in response to stored instruction signals: processor means for sequentially executing instructions as identified by instruction signals; slow access storage means accessible to the processor means through a slow memory access control means and storing manifestations of different groups of instructions and information signals; a first plurality of groups of random access storage locations for nondestructive readout copying that does not require a write-restore operation after readout, having access speed faster than said slow access storage means; a plurality of interrupt means for responding to a plurality of external interrupt signals and a plurality of internal interrupt signals; external interrupt control means connected to the interrupt means included in the plurality for providing the external interrupt signals for interrupting the group of information signals being processed by the processor means so as to cause the processor means to process a higher priority group of information signals corresponding to the highest priority external signal, said external priority being predetermined by the manner of connection of the interrupt means; supervisory means including the processor means and a supervisory program stored in the slow access storage means, for causing simultaneous processing of a plurality of groups of information signals representing computer programs on an interruptible and time-shared basis, said means including a time dividing means and internal control interrupt means included in the plurality and being responsive to said time dividing means for providing internal interrupt signals in response thereto; master program means included within said supervisory means for controlling execution of a plurality of computer problems each of which may have separate input-output operations, said master program means including means for selecting slow access storage locations to be associated with particular ones of said plurality of interrupt means; said external and said internal interrupt control means including means connected for directly accessing independently of the slow memory access means a specific slow access storage location associated with the interrupt means being responded to by said interrupt control means, said specific access storage location holding digital information representing a predetermined control state of the processor associated with such interrupt means including the location of the next instruction signal of the information group associated with such interrupt; and means for storing digital information representing the current control state of the processor in a memory location associated by the supervisory means with the respective interrupt of the plurality which responded to one of the external or internal interrupt signals, including the location of the next instruction signal associated with the group of information signals at the time processing is halted by means external to said group, so as to cause said group of information signals to resume gapless and errorless processing upon regaining access to the processor.

Claim 23

In a digital computer for processing stored and external information signals in response to stored instruction signals: processor means for sequentially executing instructions as identified by instruction signals; slow access storage means accessible to the processor means through a slow memory access control means and storing manifestations of different groups of instructions and information signals; a first plurality of groups of random access storage locations for nondestructive readout copying that does not require a write-restore operation after readout, having access speed faster than said slow access storage means; a plurality of interrupt means for responding to a plurality of external interrupt signals and a plurality of internal interrupt signals; external interrupt control means connected to the interrupt means included in the plurality for providing the external interrupt signals for interrupting the group of information signals being processed by the processor means so as to cause the processor means to process a higher priority group of information signals corresponding to the highest priority external signal, said external priority being predetermined by the manner of connection of the interrupt means; supervisory means including the processor means and a supervisory program stored in the slow access storage means, for causing simultaneous processing of a plurality of groups of information signals representing computer programs on an interruptible and time-shared basis, said means including a time dividing means and internal control interrupt means included in the plurality and being responsive to said time dividing means for providing internal interrupt signals in response thereto; master program means included within said supervisory means for controlling execution of a plurality of computer problems each of which may have separate input-output operations, said master program means including means for selecting slow access storage locations to be associated with particular ones of said plurality of interrupt means; said external and said internal interrupt control means including means connected for directly accessing independently of the slow memory access means a specific slow access storage location associated with the interrupt means being responded to by said interrupt control means, said specific access storage location holding digital information representing a predetermined control state of the processor associated with such interrupt means including the location of the next instruction signal of the information group associated with such interrupt; and means for storing digital information representing the current control state of the processor in a memory location associated by the supervisory means with the respective interrupt of the plurality which responded to one of the external or internal interrupt signals, including the location of the next instruction signal associated with the group of information signals at the time processing is halted by means external to said group, so as to cause said group of information signals to resume gapless and errorless processing upon regaining access to the processor.

Claim 24

In a digital computer for processing stored and external information signals in response to stored instruction signals as in claim 18, interrupt disable means responsive to the supervisory means for temporarily inhibiting a particular interrupt means while preserving an interrupt signal appearing at such interrupt means and its relative priority until the interrupt means is enabled.

Claim 25

In a digital computer for processing stored and external information signals in response to stored instruction signals as in claim 19, said access control means including a second plurality of fast access storage locations addressable by means of addresses corresponding to numbers within a particular range of addresses, a first portion of a location addressing signal of an instruction signal being within said range; and further including a translating means for automatically replacing said first portion of a location addressing signal of an instruction signal with the content of the fast access storagE location of the second plurality and as addressed by said first portion so as to cause the accessing means to access the location corresponding to the modified location addressing signal.

Claim 26

In a computer as set forth in claim 18, said supervisory means also including means for varying the relative priority of the plurality of interrupt means; interrupt disable means responsive to the supervisory means for temporarily inhibiting a particular interrupt means while preserving an interrupt signal appearing at such interrupt means and its elative priority until the interrupt means is enabled; interrupt disconnect means responsive to the supervisory means for temporarily rendering a particular interrupt means incapable of responding to an interrupt signal while at the same time retaining the same relative priority to other interrupt means; and register means associated with each interrupt means for controlling the interrupt disconnect means for placing the interrupt means in a waiting line according to its priority, for enabling the interrupt means once it is in the waiting line and for locking out other lower priority interrupt means after it gains access to the processor.

Claim 27

In a digital computer for processing stored and external information signals in response to stored instruction signals as in claim 18; said access control means including a second plurality of fast access storage locations addressable by means of addresses corresponding to numbers within a particular range of addresses, a first portion of a location addressing signal of an instruction signal being within said range; and further including a translating means for automatically replacing said first portion of a location addressing signal of an instruction signal with the content of the fast access storage location of the second plurality and as addressed by said first portion so as to cause the accessing means to access the location corresponding to the modified location addressing signal.

Claim 28

In a computer as set forth in claim 22, the supervisory means including means for changing the content of the second plurality of fast access storage locations so as to cause information signals to be distributed in the slow access memory in a different manner.

Claim 29

In a digital computer for processing stored and external information signals in response to stored instruction signals as in claim 22, means for selectively interpreting information signals held in the selected group of fast access storage locations as multiples and divisors of such information signals in response to a second portion of an instruction signal, and in relation to the first portion of the instruction signal to arrive at the location addressing signal as processed by the accessing means.