US3594725A
Expired / Lapsed
US
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Interlaced electronic commutator having plural subcommutators
Assignee: General Dynamics Corp
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Filing: 1968-11-04
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Granted: 1971-07-20
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Expires: 1988-11-04
Abstract
Abstract An interlaced electronic commutator system having use in a time division multiplex system. A timing circuit and a plurality of subcommutator circuits are employed, each one of which periodically gates input data for a relatively long period of time, isolates the gated input data, then gates only the last portion of the isolated input data as the subcommutator output. The outputs of all the subcommutators are then combined in a high rate pulse amplitude modulated waveform.
Inventors
- 👤 Glenn G Clinard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:50
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
291 words
An interlaced electronic commutator for commutating a number of varying analog signals comprising, a plurality of data input lines, plurality of subcommutator means each connected to said plurality of data input lines for periodically commutating data signals from said data input lines, timing means connected to said subcommutator means for supplying timing pulses in sequence to each of said subcommutator means in a repetitive periodic sequence, said timing means including a frequency source, first clock circuit means connected to said frequency source and responsive thereto, decoder means connected to said first clock circuit means and responsive thereto for applying one timing pulse at a time to each of said subcommutator means, reset pulse circuit means connected to said frequency source and to said decoder means and to each of said subcommutator means for providing a reset pulse to each of said subcommutator means, each of said subcommutator means including an isolation amplifier, an output line, first inverter circuit means connected to said timing means and responsive thereto, second clock circuit means connected to said first inverter circuit means for supplying a coded output clock signal and a synchronizing signal, first gate means connected to said second clock circuit means and to said isolation amplifier and responsive to a first one of said timing pulses from said timing means for gating a data signal in one of said data input lines to said isolation amplifier, and a second gate means connected to said timing means and to said isolation amplifier and responsive to a second one of said timing pulses from said timing means for gating the output of said isolation amplifier for the time period of said second one of said timing pulses to said output lines of said subcommutator means.
Claim 2
Dependent Claim
291 words
An interlaced electronic commutator for commutating a number of varying analog signals comprising, a plurality of data input lines, plurality of subcommutator means each connected to said plurality of data input lines for periodically commutating data signals from said data input lines, timing means connected to said subcommutator means for supplying timing pulses in sequence to each of said subcommutator means in a repetitive periodic sequence, said timing means including a frequency source, first clock circuit means connected to said frequency source and responsive thereto, decoder means connected to said first clock circuit means and responsive thereto for applying one timing pulse at a time to each of said subcommutator means, reset pulse circuit means connected to said frequency source and to said decoder means and to each of said subcommutator means for providing a reset pulse to each of said subcommutator means, each of said subcommutator means including an isolation amplifier, an output line, first inverter circuit means connected to said timing means and responsive thereto, second clock circuit means connected to said first inverter circuit means for supplying a coded output clock signal and a synchronizing signal, first gate means connected to said second clock circuit means and to said isolation amplifier and responsive to a first one of said timing pulses from said timing means for gating a data signal in one of said data input lines to said isolation amplifier, and a second gate means connected to said timing means and to said isolation amplifier and responsive to a second one of said timing pulses from said timing means for gating the output of said isolation amplifier for the time period of said second one of said timing pulses to said output lines of said subcommutator means.
Claim 3
Dependent Claim
125 words
The interlaced electronic commutator defined in claim 1, wherein said reset pulse circuit means of said tIming means includes second inverter circuit means connected to said frequency source and responsive thereto, said second inverter means having an output; third inverter circuit means connected to said subcommutator means to receive said synchronizing signal, said third inverter means having an output; fourth inverter circuit means connected to said decoder means to receive a timing pulse, said fourth inverter circuit means having an output; and NAND gate circuit means connected to said outputs of said second, third and fourth inverter circuit means and responsive to the combination input sequence from said second, third and fourth inverter circuit means for providing a gated reset pulse to said subcommutator means.
Claim 4
Dependent Claim
85 words
The interlaced electronic commutator defined in claim 1, wherein said first gate means of said subcommutator means includes a decoder circuit that decodes the output of said second clock circuit means and sequentially channels output signals; a first gate driver circuit connected to said decoder circuit and responsive to said sequentially channelled output signals; and an analog gate circuit connected to said first gate driver circuit and to said isolation amplifier, said analog gate circuit responsive to the output of said first gate driver circuit.
Claim 5
Dependent Claim
47 words
The interlaced electronic commutator defined in claim 1, wherein said second gate means of said subcommutator means includes a second gate driver circuit responsive to said timing pulses from said first clock circuit means and an output gate circuit operably connected to said second gate driver circuit.
Claim 6
Dependent Claim
21 words
The interlaced electronic commutator defined in claim 1, wherein said first clock circuit means is a 3-bit binary counter clock circuit.
Claim 7
Dependent Claim
21 words
The interlaced electronic commutator defined in claim 1, wherein said second clock circuit means is a 3-bit binary counter clock circuit.
Claim 8
Dependent Claim
18 words
The interlaced electronic commutator defined in claim 3 wherein said decoder circuit includes a plurality of NAND gates.
Claim 9
Dependent Claim
21 words
The interlaced electronic commutator defined in claim 3 wherein said plurality of analog gates each comprise a field effect transistor circuit.
Claim 10
Dependent Claim
377 words
An interlaced electronic commutator for commutating a number of varying analog signals comprising: a plurality of data input lines; a plurality of individual subcommutator means each connected to said plurality of data input lines for periodically commutating data signals from said data input lines; timing means connected to each of said subcommutator means for supplying timing pulses in sequence to each of said subcommutator means in a repetitive periodic sequence, said timing means including a frequency source, first binary counter clock circuit means connected to said frequency source and responsive thereto, decoder means connected to said first clock circuit means and responsive thereto for applying one pulse at a time to each of said subcommutator means, reset pulse circuit means connected to said frequency source and to said decoder means and to each of said subcommutator means for providing a reset pulse to each of said subcommutator means; each of said subcommutator means including an isolation amplifier; an output line; first inverter circuit means connected to said timing means and responsive to a first one of said timing pulses from said timing means; second binary counter clock circuit means connected to said inverter circuit means for supplying a coded output clock signal and a synchronizing signal; a decoder circuit connected to said second clock circuit means that decodes the output of said second clock circuit means and sequentially channels output signals; a first gate driver circuit connected to said decoder circuit and responsive to said sequentially channelled output signals; an analog gate circuit connected to said first gate driver circuit and to said isolation amplifier, said analog gate circuit responsive to the output of said first gate driver circuit for gating a data signal in one of sAid data input lines to said isolation amplifier; a second gate driver circuit connected to said timing means and responsive to a second one of said timing pulses from said timing means; and an output gate circuit operably connected to said second gate driver circuit and to said isolation amplifier and responsive to said second one of said timing pulses for gating the output of said isolation amplifier for the time period of said second one of said timing pulses to said output line of each of said subcommutator means.
Claim 11
Dependent Claim
377 words
An interlaced electronic commutator for commutating a number of varying analog signals comprising: a plurality of data input lines; a plurality of individual subcommutator means each connected to said plurality of data input lines for periodically commutating data signals from said data input lines; timing means connected to each of said subcommutator means for supplying timing pulses in sequence to each of said subcommutator means in a repetitive periodic sequence, said timing means including a frequency source, first binary counter clock circuit means connected to said frequency source and responsive thereto, decoder means connected to said first clock circuit means and responsive thereto for applying one pulse at a time to each of said subcommutator means, reset pulse circuit means connected to said frequency source and to said decoder means and to each of said subcommutator means for providing a reset pulse to each of said subcommutator means; each of said subcommutator means including an isolation amplifier; an output line; first inverter circuit means connected to said timing means and responsive to a first one of said timing pulses from said timing means; second binary counter clock circuit means connected to said inverter circuit means for supplying a coded output clock signal and a synchronizing signal; a decoder circuit connected to said second clock circuit means that decodes the output of said second clock circuit means and sequentially channels output signals; a first gate driver circuit connected to said decoder circuit and responsive to said sequentially channelled output signals; an analog gate circuit connected to said first gate driver circuit and to said isolation amplifier, said analog gate circuit responsive to the output of said first gate driver circuit for gating a data signal in one of sAid data input lines to said isolation amplifier; a second gate driver circuit connected to said timing means and responsive to a second one of said timing pulses from said timing means; and an output gate circuit operably connected to said second gate driver circuit and to said isolation amplifier and responsive to said second one of said timing pulses for gating the output of said isolation amplifier for the time period of said second one of said timing pulses to said output line of each of said subcommutator means.
Claim 12
Dependent Claim
18 words
The interlaced electronic commutator defined in claim 9, wherein said output gate circuit is a field-effect transistor circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |