US3594500A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Missile communications link
Assignee: United States Department of the Navy
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Filing: 1961-10-11
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Granted: 1971-07-20
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Expires: 1981-10-11
Abstract
Abstract The system provides for the simultaneous control of a plurality of missiles and comprises a missile receiver system for handling a large quantity of data. The receiver performs a parity check for handling an error detecting code, is able to handle phasecoded digital transmission, and contains means for distinguishing between different data signals.
Inventors
- 👤 James L James
- 👤 Hiliary H Nall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:13
CPC Classifications
F; F41; F41G; F41G7/00; F41G7/20; F41G7/30; F41G7/301; F41G7/308; G; G01; G01S; G01S7/00; G01S7/003; H; H04; H04L; H04L27/00; H04L27/18; H04L27/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
105 words
A system for receiving phase coded transmissions, comprising a receiving antenna, a pair of input delay lines, means including a differential amplifier for applying the input signal from said antenna to said input delay lines, gating means connected to said input delay lines for passing the signal from said lines only when a particular transmission is received by said system, a pair of registers connected to said input delay lines and said gating means, and a diode matrix driven by one of said registers for selecting the proper output of the system into which to channel the information stored in the other of said registers.
Claim 2
Independent Claim
105 words
A system for receiving phase coded transmissions, comprising a receiving antenna, a pair of input delay lines, means including a differential amplifier for applying the input signal from said antenna to said input delay lines, gating means connected to said input delay lines for passing the signal from said lines only when a particular transmission is received by said system, a pair of registers connected to said input delay lines and said gating means, and a diode matrix driven by one of said registers for selecting the proper output of the system into which to channel the information stored in the other of said registers.
Claim 3
Dependent Claim
45 words
A system as set forth in claim 1, wherein the connections between said gating means and said registers are randomly arranged so that the bits in the code will be interleaved in said registers thereby increasing the effectiveness of a parity check of the code.
Claim 4
Dependent Claim
41 words
A system as set forth in claim 2, further comprising a digital-analog converter ladder connected to said other register for converting digital information stored in said other register to its analog equivalent before being switched to the output of the system.
Claim 5
Dependent Claim
174 words
In a system for receiving phase coded transmissions, an antenna for receiving a phase coded signal, a pair of input delay lines containing a plurality of taps, means including a difference amplifier for converting said signal into a pair of complementary pulse codes and for applying said pulse codes to said input delay lines, a pair of registers, a plurality of first AND-gates connecting one of said input delay lines to said pair of registers, an OR-gate and a second AND-gate, a plurality of switches connecting the taps on said delay lines to said OR-gate and said second AND-gate according to a prearranged pattern, an INHIBIT-gate, said OR-gate and said second AND-gate being connected to said INHIBIT-gate such that a signal will pass from said second AND-gate through said INHIBIT-gate as long as no signal is derived from said OR-gate, a timing delay line for receiving a pulse from said INHIBIT-gate, said timing delay line operating to trigger said first AND-gates so as to pass said pulse codes to said registers in predetermined groups.
Claim 6
Dependent Claim
174 words
In a system for receiving phase coded transmissions, an antenna for receiving a phase coded signal, a pair of input delay lines containing a plurality of taps, means including a difference amplifier for converting said signal into a pair of complementary pulse codes and for applying said pulse codes to said input delay lines, a pair of registers, a plurality of first AND-gates connecting one of said input delay lines to said pair of registers, an OR-gate and a second AND-gate, a plurality of switches connecting the taps on said delay lines to said OR-gate and said second AND-gate according to a prearranged pattern, an INHIBIT-gate, said OR-gate and said second AND-gate being connected to said INHIBIT-gate such that a signal will pass from said second AND-gate through said INHIBIT-gate as long as no signal is derived from said OR-gate, a timing delay line for receiving a pulse from said INHIBIT-gate, said timing delay line operating to trigger said first AND-gates so as to pass said pulse codes to said registers in predetermined groups.
Claim 7
Dependent Claim
50 words
In a system as set forth in claim 4, wherein one end of said pair of input delay lines is connected to said INHIBIT-gate so as to prevent operation of said gate so long as coded infoRmation is present in said one end of said pair of input delay lines.
Claim 8
Independent Claim
195 words
A system for receiving phase coded transmissions, comprising an antenna for receiving a phase coded signal, waveguide means for converting said signal into a pair of complementary amplitude-modulated pulse codes, a first gating means for identifying said coded transmission, switch means for applying a portion of said transmission to said first gating means, means including a pair of delay lines for transferring bits of said code from said waveguide to said switch means in predetermined groups, a second gating means for passing a signal from said first gating means to a timing delay line only when a particular transmission is received by said system, a plurality of fourth gating means connected to said switching means for passing the input pulses from one of said pair of delay lines only in response to a trigger pulse from said timing delay line, a pair of registers for receiving and storing data from said fourth gating means, and a diode matrix driven by one of said registers for selecting the proper output of the system into which to channel the information stored in the other of said registers in response to a trigger from said timing delay line.
Claim 9
Independent Claim
195 words
A system for receiving phase coded transmissions, comprising an antenna for receiving a phase coded signal, waveguide means for converting said signal into a pair of complementary amplitude-modulated pulse codes, a first gating means for identifying said coded transmission, switch means for applying a portion of said transmission to said first gating means, means including a pair of delay lines for transferring bits of said code from said waveguide to said switch means in predetermined groups, a second gating means for passing a signal from said first gating means to a timing delay line only when a particular transmission is received by said system, a plurality of fourth gating means connected to said switching means for passing the input pulses from one of said pair of delay lines only in response to a trigger pulse from said timing delay line, a pair of registers for receiving and storing data from said fourth gating means, and a diode matrix driven by one of said registers for selecting the proper output of the system into which to channel the information stored in the other of said registers in response to a trigger from said timing delay line.
Claim 10
Dependent Claim
45 words
A system as set forth in claim 6, wherein the connections between said fourth gating means and said registers are randomly arranged so that the code bits will be interleaved in said registers, thereby increasing the effectiveness of a parity check of the code received.
Claim 11
Independent Claim
119 words
A system for receiving phase coded transmissions, comprising an antenna for receiving a phase coded digital signal, a pair of input delay lines, means including a differential amplifier for applying the input signal from said antenna to said input delay lines, gating means connected to said delay lines for passing only certain select transmissions, a pair of registers connected to said delay lines via said gating means, a first diode matrix driven by one of said registers for selecting the proper output of the system into which to channel the information stored in the other of said registers, and a second diode matrix connected to said other register for activating additional outputs when pulsed by said first diode matrix.
Claim 12
Independent Claim
119 words
A system for receiving phase coded transmissions, comprising an antenna for receiving a phase coded digital signal, a pair of input delay lines, means including a differential amplifier for applying the input signal from said antenna to said input delay lines, gating means connected to said delay lines for passing only certain select transmissions, a pair of registers connected to said delay lines via said gating means, a first diode matrix driven by one of said registers for selecting the proper output of the system into which to channel the information stored in the other of said registers, and a second diode matrix connected to said other register for activating additional outputs when pulsed by said first diode matrix.
Claim 13
Dependent Claim
45 words
A system as set forth in claim 8, wherein the connections between said gating means and said registers are randomly arranged so that the bits in the code will be interleaved in said registers thereby increasing the effectiveness of a parity check of the code.
Claim 14
Dependent Claim
44 words
A system as set forth in claim 9, further comprising a digital-analog converter ladder connected to said other register for converting the digital information stored in said other register to its analog equivalent prior to its being switched to the output of said system.
Claim 15
Dependent Claim
86 words
A system as set forth in claim 8, wherein said gating means comprises a plurality of first AND-gates connecting one of said input delay lines to said pair of registers, an OR-gate and a second AND-gate, a plurality of switches connecting said delay lines to said OR-gate and said second AND-gate according to a prearranged pattern, an INHIBIT-gate, said OR-gate and said second AND-gate being connected to said INHIBIT-gate, and a timing delay line connected to said INHIBIT-gate for controlling the operation of said first AND-gates.
References Cited (Backward Citations)
US2946044A
Cited
US2933364A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |