US3593283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Feature-extracting system for pattern-recognition apparatus and the like
Assignee: Hitachi Ltd
•
Filing: 1967-09-19
•
Granted: 1971-07-13
•
Expires: 1987-09-19
Abstract
Abstract This specification discloses a feature-extracting system for the use in so-called pattern-recognizing apparatus and the like. The system is provided with a memory composed of a number of memorizing circuits arranged in matrix form, each of which is selectively electrically coupled with the adjoining memorizing circuits. When a pattern to be recognized is memorized in the memory by means of partial features thereof and the memorizing circuits are scanned sequentially, all of the circuits which memorize a partial figure of the pattern are caused to invert in chain reaction. By counting a counting signal produced only when an initial one of the memorizing circuits which have memorized the quantized partial features of the partial figures of the pattern is scanned, it is possible to determine the number of partial figures forming the pattern to be recognized.
Inventors
- 👤 Yoshikazu Miyamoto
- 👤 Masao Hibi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:13
CPC Classifications
G; G06; G06V; G06V30/00; G06V30/10; G06V30/18; G06V30/1801; G06V30/18076
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
275 words
A feature-extracting system for pattern-recognizing apparatus and the like which comprises: memory means comprised of a number of memorizing circuits for memorizing quantized partial feature signals of a pattern to be extracted, each of said memorizing circuits including a first input terminal for receiving a quantized partial feature signal for storage so as to be placed into a storing state upon receipt of a quantized partial feature signal, a second input terminal for receiving a readout order signal so that a memorizing circuit is reset from the storing state when it has stored therein a quantized partial feature signal and at least one output terminal for providing an output signal only when said circuit has stored therein a quantized partial feature signal by said circuit and in response to receipt of a readout order signal thereby; processing means for supplying quantized partial feature signals of a pattern to the first input terminals of said respective memorizing circuits selectively; scanning means for sequentially supplying a readout order signal to the second input terminal of each said memorizing circuit to scan said memory means; coupling means for selectively electrically coupling the output terminal of each said memorizing circuit with the second input terminals of a limited number of the other memorizing circuits adjoining thereto, whereby the output signal of the former circuit is introduced to the second input terminals of the latter circuits as a readout order signal; and output means connected to the output terminal of each memorizing circuit for providing a counting signal only when a readout order signal from said scanning means is applied to said memorizing circuit storing a quantized partial feature signal.
Claim 2
Dependent Claim
275 words
A feature-extracting system for pattern-recognizing apparatus and the like which comprises: memory means comprised of a number of memorizing circuits for memorizing quantized partial feature signals of a pattern to be extracted, each of said memorizing circuits including a first input terminal for receiving a quantized partial feature signal for storage so as to be placed into a storing state upon receipt of a quantized partial feature signal, a second input terminal for receiving a readout order signal so that a memorizing circuit is reset from the storing state when it has stored therein a quantized partial feature signal and at least one output terminal for providing an output signal only when said circuit has stored therein a quantized partial feature signal by said circuit and in response to receipt of a readout order signal thereby; processing means for supplying quantized partial feature signals of a pattern to the first input terminals of said respective memorizing circuits selectively; scanning means for sequentially supplying a readout order signal to the second input terminal of each said memorizing circuit to scan said memory means; coupling means for selectively electrically coupling the output terminal of each said memorizing circuit with the second input terminals of a limited number of the other memorizing circuits adjoining thereto, whereby the output signal of the former circuit is introduced to the second input terminals of the latter circuits as a readout order signal; and output means connected to the output terminal of each memorizing circuit for providing a counting signal only when a readout order signal from said scanning means is applied to said memorizing circuit storing a quantized partial feature signal.
Claim 3
Dependent Claim
27 words
The feature-extracting system according to claim 1, wherein said memory means is a means for memorizing noninverted quantized partial feature signals of the pattern to be extracted.
Claim 4
Dependent Claim
27 words
The feature-extracting system according to claim 1 wherein said memory means is a means for memorizing inverted quantized partial feature signals of the pattern to be extracted.
Claim 5
Dependent Claim
38 words
The feature-extracting system according to claim 1 wherein said output means further includes counting means for counting the number of counting signals for the period during which all of said memorizing circuits are scanned by said scanning means.
Claim 6
Dependent Claim
71 words
The feature-extracting system according to claim 1 wherein said memory means is comprised of at least first and second groups of said memorizing circuits connected to said processing means, one of said first and second groups being for memorizing quantized partial feature signals of the pattern to be extracted derived from said processing means, and the other one for memorizing inverted quantized partial feature signals thereof derived from said processing means.
Claim 7
Dependent Claim
54 words
The feature-extracting system according to claim 5 wherein said output means further includes first and second counting means connected to said first and second groups of memorizing circuits, respectively, for counting the number of counting signals derived therefrom for the period during which all of said memorizing circuits are scanned by said scanning means.
Claim 8
Dependent Claim
58 words
The feature-extRacting system according to claim 1 wherein said memory means is composed of plural groups of said memorizing circuits connected to said processing means, at least one of which is connected with another one of said groups for transferring signals inverted with respect to the quantized partial feature memorized in the former group to the latter group.
Claim 9
Dependent Claim
81 words
The feature-extracting system according to claim 1 wherein said memorizing circuits comprise: a capacity element connected with said first input terminal for storing said partial feature signal; a switching element connected across said capacity element for selectively discharging the capacity element; means for controlling conductivity of said switching element in response to said readout order signal supplied from said second input terminal; and means detecting variation in current through said switching element for supplying an output signal to said output terminal.
Claim 10
Dependent Claim
16 words
The feature-extracting system according to claim 8 wherein said switching element consists of a discharge tube.
Claim 11
Dependent Claim
17 words
The feature-extracting system according to claim 8 wherein said switching element consists of a silicon controlled rectifier.
Claim 12
Dependent Claim
37 words
The feature-extracting system according to claim 8 wherein said memorizing circuits further comprise an additional switching element connected across said capacity element for discharging the element, and means for actuating said additional element by a reset signal.
Claim 13
Dependent Claim
22 words
The feature-extracting system according to claim 11 wherein said additional switching element consists of an electrical relay actuated by said reset signal.
Claim 14
Dependent Claim
24 words
The feature-extracting system according to claim 11 wherein said additional switching element is composed of a silicon controlled rectifier actuated by said reset signal.
Claim 15
Dependent Claim
137 words
The feature-extracting system according to claim 1 wherein said memorizing circuits comprise: a first series circuit consisting of an electrical source, a transistor, a first silicon controlled rectifier and a first resistor; a second series circuit consisting of a second silicon controlled rectifier and a second resistor, connected across said first resistor; means for supplying a control signal to the control electrode of said transistor to control conductivity thereof; means for supplying said feature signal from said first input terminal to a control terminal of said first rectifier to control conductivity thereof; means for supplying said readout order signal from said second input terminal to a control terminal of said second rectifier to control conductivity thereof; and means for detecting a variation in current through said second rectifier to supply an output signal to said output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-12 | 1975-01-11 | 1975-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-12 | 1979-01-11 | 1979-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-12 | 1983-01-11 | 1983-07-13 | $7700.00 | Window Closed / Lapsed |