Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
In an automatic error correcting telecommunication system for multielement binary code signals having a transmitter and a receiver and the automatic error detecting and correcting means for disturbed signals at the receiver, requesting their repetition from the transmitter, and stopping the transmission of further signals until the disturbed signal has been received undisturbed, the improvement comprising: a device for reducing the delay caused by this repetition, comprising: at said transmitter and said receiver; a. means (KZA, KOA) for speeding up the rate of transmission of said signals and producing a first series of pulses at this faster rate (Vfa), b. means (MZ, MO) for generating a second series of pulses from said first series of pulses at the normal slower rate (Va) at which the signals are printed at said receiver, and c. memory means (ZR, OR) for storing signals controlled in part by said means for generating said second series of pulses; and at said transmitter: d. a differential counter (N) for counting a number corresponding to the maximum number of signals which can be stored in the memory means at said receiver, which counter is controlled by both said series of pulses to prevent transmission of more signals than can be stored in said memory means at said receiver.
Claim 2
Dependent Claim
211 words
In an automatic error correcting telecommunication system for multielement binary code signals having a transmitter and a receiver and the automatic error detecting and correcting means for disturbed signals at the receiver, requesting their repetition from the transmitter, and stopping the transmission of further signals until the disturbed signal has been received undisturbed, the improvement comprising: a device for reducing the delay caused by this repetition, comprising: at said transmitter and said receiver; a. means (KZA, KOA) for speeding up the rate of transmission of said signals and producing a first series of pulses at this faster rate (Vfa), b. means (MZ, MO) for generating a second series of pulses from said first series of pulses at the normal slower rate (Va) at which the signals are printed at said receiver, and c. memory means (ZR, OR) for storing signals controlled in part by said means for generating said second series of pulses; and at said transmitter: d. a differential counter (N) for counting a number corresponding to the maximum number of signals which can be stored in the memory means at said receiver, which counter is controlled by both said series of pulses to prevent transmission of more signals than can be stored in said memory means at said receiver.
Claim 3
Dependent Claim
19 words
A system according to claim 1 wherein said means for generating said second series of pulses comprises a multivibrator.
Claim 4
Dependent Claim
39 words
A system according to claim 1 wherein said memory means at said receiver comprises a plurality of triggers (A1-E5), gates (IV), and shift register (F1-F5, S) for storing each element of each of the number of signals stored therein.
Claim 5
Dependent Claim
28 words
A system according to claim 3 wherein said triggers include a trigger (P) for producing stop and start elements for each signal before being conducted to the printer.
Claim 6
Dependent Claim
18 words
A system according to claim 3 including a multivibrator (M) for producing pulses for controlling said shift register.
Claim 7
Dependent Claim
56 words
A system according to claim 1 including a gate means (G1) between said transmitter memory means and said means for speeding up the rate of transmission controlled by said differential counter, said gate means controlling said transmitter to stop said transmitter and transmit an idle time signal when said counter reaches said maximum number of signals.