Synchronous read clock apparatus

Claim 3

comparing the phase between the derived reference signal and each of the pulses of said data train at predetermined ones of said reference points and deriving an error signal proportional to differences in phase therebetween;

Claim 4

comparing the phase between the derived reference signal and each of the pulses of said data train at predetermined ones of said reference points and deriving an error signal proportional to differences in phase therebetween;

Claim 7

comparing the phase between the derived symmetrical periodic reference signal and each of the pulses of said input data to derive an error signal proportional to the differences in phase therebetween;

Claim 8

comparing the phase between the derived symmetrical periodic reference signal and each of the pulses of said input data to derive an error signal proportional to the differences in phase therebetween;

Claim 9

adjusting at a predetermined exponential rate the phase of the reference signal in accordance with said error signal, said rate being selected to establish a phase quadrature relationship between the pulses of the data train and said period reference signal and,

Claim 10

adjusting at a predetermined exponential rate the phase of the reference signal in accordance with said error signal, said rate being selected to establish a phase quadrature relationship between the pulses of the data train and said period reference signal and,

Claim 11

adjusting at a predetermined rate the frequency of the reference signal in accordance with said error signal to establish a predetermined phase relationship between said reference signal and said input data train pulses;

Claim 12

adjusting at a predetermined rate the frequency of the reference signal in accordance with said error signal to establish a predetermined phase relationship between said reference signal and said input data train pulses;

Claim 15

delaying the input data train to align the leading edge of said pulses with said predetermined ones of said reference points; and

Claim 16

delaying the input data train to align the leading edge of said pulses with said predetermined ones of said reference points; and

Claim 17

deriving from predetermined points of said reference signal pulses of said timing train with maximum out of phase relationship to the pulses of said input data train for facilitating recovery of information therefrom.

Claim 18

deriving from predetermined points of said reference signal pulses of said timing train with maximum out of phase relationship to the pulses of said input data train for facilitating recovery of information therefrom.

Claim 19

The apparatus of claim 3 wherein said integrating means consists of serially connected resistive capacitive elements connected to provide a time constant for producing a magnitude of correction voltage whose rate of change adjusts said frequency of said resonant tank circuit means to establish said phase quadrature relationship at a critically damped rate.

Claim 20

deriving from said reference signal said timing train from different ones of said reference points alternately to said predetermined ones for maintaining maximum separation between the data and synch pulses of said input data train and said timing train pulses for facilitating subsequent recovering of information signals from said data train.

Claim 21

deriving from said reference signal said timing train from different ones of said reference points alternately to said predetermined ones for maintaining maximum separation between the data and synch pulses of said input data train and said timing train pulses for facilitating subsequent recovering of information signals from said data train.

Claim 22

The apparatus of claim 3 wherein said phase error generating means includes phase comparator means connected to receive the pulses of said data train and said sinusoidal reference signal respectively; and amplifier means connected in series with said phase comparator means and said integrating means, said amplifier means connected to apply to said integrating means in the absence of an error voltage, a reference voltage of a predetermined magnitude and polarity for conditioning said resonant tank circuit means to generate said sinusoidal signal at a nominal frequency and being further adapted to vary magnitude of said reference voltage in accordance with said error voltage.

Claim 23

The apparatus of claim 3 wherein said resonant circuit means consists of a parallel resonant tank circuit whose nominal resonant frequency corresponds to the frequency of data pulses, said parallel resonant tank circuit including a voltage-variable capacitor means, said capacitor means connected to receive said correction bias voltage for changing the capacitance thereof and adjusting the frequency of said resoNant circuit means at a critically damped rate.

Claim 24

Apparatus of claim 3 wherein said resonant circuit means includes resistive capacitive and inductive elements, said elements elected to provide said Q for decreasing the amplitude of said sinusoidal reference signal upon the absence of a successive predetermined number of pulses in said data train to a magnitude sufficient to inhibit said level switching and pulse generating means from deriving further pulses of said timing train from said reference points of said sinusoidal reference signal.

Claim 25

Read clock apparatus for use in a magnetic memory system for facilitating detection of information contained in a data train derived from double frequency recorded binary signals which include a synch data bit at the beginning of each interval and a data bit substantially in the midpoint of each interval wherein such synch bits and data bits are subject to both frequency and phase shift, said read clock apparatus comprising; normally inactive oscillatory means included within said read clock for generating in response to pulses of said data train applied from said memory system a symmetrical periodic reference signal including a number of reference points; error signal generating and correcting means coupled to said normally inactive oscillatory means for producing an error signal whose magnitude is proportional to the phase displacement between said pulses of said data train relative to predetermined ones of said reference points, said error signal generating and correction means connected to apply an error signal voltage to said oscillatory means to adjust the frequency thereof whereby said phase displacement is decreased at a predetermined exponential rate; delay means for delaying said data train a predetermined amount for aligning the pulses thereof with said predetermined ones of said reference points of said reference signal; and level switching and pulse generating means for deriving an output timing train from alternate points of said reference signal.

Claim 26

Read clock apparatus for use in a magnetic memory system for facilitating detection of information contained in a data train derived from double frequency recorded binary signals which include a synch data bit at the beginning of each interval and a data bit substantially in the midpoint of each interval wherein such synch bits and data bits are subject to both frequency and phase shift, said read clock apparatus comprising; normally inactive oscillatory means included within said read clock for generating in response to pulses of said data train applied from said memory system a symmetrical periodic reference signal including a number of reference points; error signal generating and correcting means coupled to said normally inactive oscillatory means for producing an error signal whose magnitude is proportional to the phase displacement between said pulses of said data train relative to predetermined ones of said reference points, said error signal generating and correction means connected to apply an error signal voltage to said oscillatory means to adjust the frequency thereof whereby said phase displacement is decreased at a predetermined exponential rate; delay means for delaying said data train a predetermined amount for aligning the pulses thereof with said predetermined ones of said reference points of said reference signal; and level switching and pulse generating means for deriving an output timing train from alternate points of said reference signal.

Claim 27

A read clock apparatus for generating a timing pulse train for recovery of information of an encoded input data train derived from double frequency recorded binary signals received from an random access memory means wherein said data train is preceded by a predetermined number of pulses for synchronizing said read clock apparatus with said data train, said read clock apparatus comprising; means for reshaping the pulses of said data train; a normally inactive resonant tank circuit means including a voltage frequency sensitive element, said resonant tank circuit means coupled to said reshaping means and operative in response to the pulses of said data train to generate a periodic symmetrical reference signal including a plurality of crossover points; error generating and correction means connected to receive said reshaped data train and said periodic reference signal, said error generating and correction means including phase comparator means for generating an error voltage whose magnitude is proportional to the difference in phase between each of the pulses of said pulse train and said reference signal and integrating means connected with said phase comparator means, said integrating means connected to generate in response to said error voltage a correction voltage for application to said voltage frequency sensitive element for varying the frequency of said resonant tank circuit means at a rate for minimizing the number of synchronizing pulses required to synchronize said read clock apparatus; impedance matching means connected to said resonant tank circuit means, the impedance of said impedance matching means in parallel with the frequency elements of said resonant tank circuit means selected to provide a predetermined circuit Q; delay means connected to said reshaping means for delaying said data train to align said data train to coincide with predetermined ones of said crossover points; and level switching and pulse generating means connected to said impedance means for receiving said periodic reference signal, said level switching and pulse generating means operative to derive from different ones of said crossover points said timing pulse train.

Claim 28

A read clock apparatus for generating a timing pulse train for recovery of information of an encoded input data train derived from double frequency recorded binary signals received from an random access memory means wherein said data train is preceded by a predetermined number of pulses for synchronizing said read clock apparatus with said data train, said read clock apparatus comprising; means for reshaping the pulses of said data train; a normally inactive resonant tank circuit means including a voltage frequency sensitive element, said resonant tank circuit means coupled to said reshaping means and operative in response to the pulses of said data train to generate a periodic symmetrical reference signal including a plurality of crossover points; error generating and correction means connected to receive said reshaped data train and said periodic reference signal, said error generating and correction means including phase comparator means for generating an error voltage whose magnitude is proportional to the difference in phase between each of the pulses of said pulse train and said reference signal and integrating means connected with said phase comparator means, said integrating means connected to generate in response to said error voltage a correction voltage for application to said voltage frequency sensitive element for varying the frequency of said resonant tank circuit means at a rate for minimizing the number of synchronizing pulses required to synchronize said read clock apparatus; impedance matching means connected to said resonant tank circuit means, the impedance of said impedance matching means in parallel with the frequency elements of said resonant tank circuit means selected to provide a predetermined circuit Q; delay means connected to said reshaping means for delaying said data train to align said data train to coincide with predetermined ones of said crossover points; and level switching and pulse generating means connected to said impedance means for receiving said periodic reference signal, said level switching and pulse generating means operative to derive from different ones of said crossover points said timing pulse train.