Variable frequency pulse generator

Claim 2

Variable timing apparatus, said apparatus having a plurality of associated stages for use with digital devices and wherein each of said stages includes: means for receiving incoming signal pulses; means operatively associated with said receiving means for delaying said incoming pulses; means joined to said delay means for determining the extent of said delay; means connected to said delay determining means for producing output timing pulses in response to the delayed incoming signal pulses; and means for coupling said output timing pulses with the delay determining means of the preceding stage to control the time duration of the output timing pulses from said preceding stage.

Claim 3

Variable timing apparaTus as in claim 1 wherein said delay determining means is operatively associated with all of said stages to enable the determination of the extent of said delay for all stages.

Claim 4

Variable timing apparatus as in claim 1 wherein said delay means is tapped to provide a plurality of delay times to said incoming signals.

Claim 5

Variable timing apparatus as in claim 3 wherein said determining means include: a plurality of AND gates in circuit with said delay means to receive the delayed pulses from said delay means and to provide input signals to said producing means.

Claim 6

Variable timing apparatus as in claim 4 wherein said determining means further include: at least one OR gate in circuit with the outputs of said AND gates and associated with said producing means for providing signals to said producing means.

Claim 7

Variable timing apparatus as in claim 5 wherein said determining means further include: a first flip-flop, the outputs of which are in circuit with a first grouping of said AND gates; a second flip-flop, the outputs of which are in circuit with a second grouping of said AND gates; and switch means associated with said first and second flip-flops for selectively determining the output characteristics of said flip-flops.

Claim 8

Variable timing apparatus as in claim 6 wherein said flip-flops are in circuit with each of said plurality of stages of said apparatus.

Claim 9

Variable timing apparatus as in claim 7 wherein certain of said AND gates are respectively coupled to each of said delay taps and wherein at least one additional one of said AND gates is coupled to an output of said output timing pulse producing means to selectively latch on said output timing pulse.

Claim 10

Variable timing apparatus as in claim 6 wherein said switch means is a three position switch including: a movable grounded contact; a first input in circuit with said first flip-flop to be engaged by said movable contact when said apparatus is to be operated in a fast mode; a second input in circuit with said second flip-flop to be engaged by said moveable contact when said apparatus is to be operated in a slow mode; said movable contact being positioned in a third position when said apparatus is to be operated in a normal mode.

Claim 11

Operatively variable timing device having a plurality of associated stages for use in combination with a digital device device a plurality of functional units, wherein one of said variable timing devices is respectively associated with each of said functional units to control the speed of operation thereof and wherein each stage of said timing devices include: means for receiving incoming signal pulses; delay means operatively associated with said receiving means for providing variable delays to said incoming signal pulses; a plurality of AND gates, each one operatively associated to receive said signal pulses from a predetermined delay; switching means associated with said plurality of AND gates to determine the gating thereof and to determine at what speed said device and said associated functional unit will operate; output means associated with said plurality of AND gates for providing output timing pulses of selected duration and frequency as at least partially determined by said switching means; a latching circuit associated with said AND gates of said stage and said output means of said stage for latching on each of said output timing pulses from said stage; means for enabling the termination of said output timing pulses from said stage upon the initiation of respective output timing pulses from said output means of the following stage.

Claim 12

Operatively variable timing device having a plurality of associated stages for use in combination with a digital device device a plurality of functional units, wherein one of said variable timing devices is respectively associated with each of said functional units to control the speed of operation thereof and wherein each stage of said timing devices include: means for receiving incoming signal pulses; delay means operatively associated with said receiving means for providing variable delays to said incoming signal pulses; a plurality of AND gates, each one operatively associated to receive said signal pulses from a predetermined delay; switching means associated with said plurality of AND gates to determine the gating thereof and to determine at what speed said device and said associated functional unit will operate; output means associated with said plurality of AND gates for providing output timing pulses of selected duration and frequency as at least partially determined by said switching means; a latching circuit associated with said AND gates of said stage and said output means of said stage for latching on each of said output timing pulses from said stage; means for enabling the termination of said output timing pulses from said stage upon the initiation of respective output timing pulses from said output means of the following stage.