Facsimile communication control circuit

Claim 2

In a voice-graphic communication facsimile transceiver system wherein voice and graphic information is transmitted and received, a control circuit at each transceiver in said system comprising first switch means for selectively switching said transceiver into voice and graphic operation modes respectively, second switch means for selectively switching said transceiver into transmit and receive operation modes respectively, control logic means responsive to the respective condition of said first and second switch means for selectively operating said transceiver in said selected operation modes, and means for selectively transmitting and receiving voice and graphic information in accordance with said predetermined switching functions.

Claim 3

A circuit as defined in claim 1 above further including means for injecting a stop tone signal prior to the transmission of the information in the transmit and graphic modes, means for detecting said stop tone signal from the transmitted information in the receive and graphic modes, and means responsive to said stop tone signal detection for conditioning the transceiver into the receive mode.

Claim 4

A circuit as defined in claim 2 above wherein said control logic means comprises first plurality of logic circuit means enabled in the transmit mode and disabled in the receive mode, second plurality of logic circuit means enabled in the receive mode and disabled in the transmit mode, whereby said transceiver is conditioned to operate in said predetermined operational modes.

Claim 5

A circuit as defined in claim 3 above further including quantizing means for converting said graphic information into synchronous digital signals for application by said control logic means.

Claim 6

In a graphic communication scanner and printer transceiver system wherein digital information signals are transmitted and received, control logic circuitry comprising first gating means for gating said digital information signals in response to an enabling signal in the transmit mode, said first gating means being disabled in the receive mode, second gating means for gating a reverse supervisory logic level shift in response to an enabling signal in the receive mode, said second gating means being disabled in the transmit mode, third gating means for gating a printer interlock signal in response to an enabling signal in the receive mode, said third gating means being disabled in the transmit mode, fourth gating means for gating a carrier detect signal in response to received data in the receive mode, said fourth gating means being disabled in the transmit mode, fifth gating means for gating a stop tone injection signal in response to an enabling signal in the transmit mode, said fifth gating means being disabled in the receive mode, and sixth gating means for inhibiting said stop tone injection signal in response to an enabling signal in the receive mode, said sixth gating means being disabled in the transmit mode, whereby said transceiver is selectively operated in transmit and receive modes in accordance with said enabling signals.

Claim 7

In a graphic communication scanner and printer transceiver system wherein digital information signals are transmitted and received, control logic circuitry comprising first gating means for gating said digital information signals in response to an enabling signal in the transmit mode, said first gating means being disabled in the receive mode, second gating means for gating a reverse supervisory logic level shift in response to an enabling signal in the receive mode, said second gating means being disabled in the transmit mode, third gating means for gating a printer interlock signal in response to an enabling signal in the receive mode, said third gating means being disabled in the transmit mode, fourth gating means for gating a carrier detect signal in response to received data in the receive mode, said fourth gating means being disabled in the transmit mode, fifth gating means for gating a stop tone injection signal in response to an enabling signal in the transmit mode, said fifth gating means being disabled in the receive mode, and sixth gating means for inhibiting said stop tone injection signal in response to an enabling signal in the receive mode, said sixth gating means being disabled in the transmit mode, whereby said transceiver is selectively operated in transmit and receive modes in accordance with said enabling signals.

Claim 8

A control circuit comprising first and second input terminals, a first AND gate with its inputs coupled to said first and second input terminals, a third input terminal, a second AND gate with its inputs coupled to said third and inverted second input terminals, a first output terminal coupled to the common output from said first and second AND gates, a fourth input terminal, a third AND gate with its inputs coupled to said fourth and inverted second input terminal, A fifth input terminal, a fourth AND gate with its inputs coupled to said second and fifth input terminals, a fifth AND gate with one input coupled to the common output from said third and fourth AND gates and the other input to said third input terminal, a second output terminal coupled to the output from said fifth AND gate, a sixth AND gate with its inputs coupled to said second input terminal and the common output of said third and fourth AND gates, a seventh AND gate with its inputs coupled to the inverted common outputs from said third and fourth AND gates and the inverted input from said second input terminal, a third output terminal coupled to said inverted common output from said third and fourth AND gates, a flip-flop circuit coupled to the outputs of said sixth and seventh AND gates, means for enabling said first, fourth, and sixth AND gates in one mode, and means for enabling said second, third, fifth and seventh AND gates in the other mode, thereby logically operating on selected inputs to the input terminals in either of said selected modes.

Claim 9

A control circuit comprising first and second input terminals, a first AND gate with its inputs coupled to said first and second input terminals, a third input terminal, a second AND gate with its inputs coupled to said third and inverted second input terminals, a first output terminal coupled to the common output from said first and second AND gates, a fourth input terminal, a third AND gate with its inputs coupled to said fourth and inverted second input terminal, A fifth input terminal, a fourth AND gate with its inputs coupled to said second and fifth input terminals, a fifth AND gate with one input coupled to the common output from said third and fourth AND gates and the other input to said third input terminal, a second output terminal coupled to the output from said fifth AND gate, a sixth AND gate with its inputs coupled to said second input terminal and the common output of said third and fourth AND gates, a seventh AND gate with its inputs coupled to the inverted common outputs from said third and fourth AND gates and the inverted input from said second input terminal, a third output terminal coupled to said inverted common output from said third and fourth AND gates, a flip-flop circuit coupled to the outputs of said sixth and seventh AND gates, means for enabling said first, fourth, and sixth AND gates in one mode, and means for enabling said second, third, fifth and seventh AND gates in the other mode, thereby logically operating on selected inputs to the input terminals in either of said selected modes.