Extended aperture deltic correlator

Claim 1

A system of cascaded Deltic correlators having an aperture of increased size comprising, in combination, a first and second Deltic correlator, each Deltic correlator having a first delay line, a first gate connected to the input of said first delay line, a second gate connected in a first feedback circuit of said delay line, and a first 1-bit register connected to the output of said first delay line, each Deltic correlator also having a second delay line, a third gate connected to the input of said second delay line, a fourth gate connected in a first feedback circuit of said second delay line, a second 1-bit register connected to the output of said second delay line, and a fifth gate in series with said second register in a second feedback circuit of said second delay line, each Deltic correlator also having means for coupling sampling pulses to the first, second, third, fourth gates so as to periodically open each first and third gate and close each second and fourth gate; means for connecting the output of the first 1-bit register of said first Deltic correlator to the first gate of said second Deltic correlator; means for coupling a binary input signal to the first gate of said first Deltic correlator; means for also coupling sampling pulses to the first 1-bit register of said first Deltic correlator so as to periodically transfer the count stored therein to the first gate of said second Deltic correlator as an input signal to this Deltic correlator, each of said delay lines having a time delay slightly shorter than the time interval between sampling pulses, whereby pulse length portions of said binary input signal are fed into the first delay line of said first Deltic correlator with each of these pulses thereafter circulating around its first feedback path until a particular pulse coincides with a sampling pulse at said second gate, each of these pulses also passing into the first register of said first Deltic correlator and then, at the time of occurrence of the next sampling pulse, through the first gate of said second Deltic correlator into the first delay line of said second Deltic correlator and thereafter circulating around its first feedback until a particular pulse coincides with the appearance of a sampling pulse at the first gate of said second Deltic correlator, said pulses being time compressed because of the length of the delay lines compared to the time interval between sampling pulses whereby complementary time compressed input signal pulse trains representing adjacent portions of said input signal appear in the output of the first delay lines of said Deltic correlators; means for connecting a reference signal to the third gate of said first Deltic correlator; means for connecting the output of the second 1-bit register of said first Deltic correlator to the first gate of said second Deltic correlator; means for additionally controlling the operation of the third, fourth and fifth gates and said second 1-bit registers such that either a first mode of operation is obtained wherein the time compressed reference signal pulse trains which appear in the output of the second delay of said Deltic correlators represent the same adjacent portions of said reference signal or a second mode of operation is obtained wherein these signal pulse trains represent changing adjacent portions of said reference signal, each Deltic correlator also having means for multiplying the time compressed pulse trains appearing in the output of its first and second delay lines and for integrating the results thereof to obtain an output signal whose amplitude is indicative of the correlation between those portions of the input and reference signal which are represented by these pulse trains; and means for combining the output signals from each Deltic correlator to give an overall output signal for the cascaded system.

Claim 2

A system of cascaded Deltic correlators having an aperture of increased size comprising, in combination, a first and second Deltic correlator, each Deltic correlator having a first delay line, a first gate connected to the input of said first delay line, a second gate connected in a first feedback circuit of said delay line, and a first 1-bit register connected to the output of said first delay line, each Deltic correlator also having a second delay line, a third gate connected to the input of said second delay line, a fourth gate connected in a first feedback circuit of said second delay line, a second 1-bit register connected to the output of said second delay line, and a fifth gate in series with said second register in a second feedback circuit of said second delay line, each Deltic correlator also having means for coupling sampling pulses to the first, second, third, fourth gates so as to periodically open each first and third gate and close each second and fourth gate; means for connecting the output of the first 1-bit register of said first Deltic correlator to the first gate of said second Deltic correlator; means for coupling a binary input signal to the first gate of said first Deltic correlator; means for also coupling sampling pulses to the first 1-bit register of said first Deltic correlator so as to periodically transfer the count stored therein to the first gate of said second Deltic correlator as an input signal to this Deltic correlator, each of said delay lines having a time delay slightly shorter than the time interval between sampling pulses, whereby pulse length portions of said binary input signal are fed into the first delay line of said first Deltic correlator with each of these pulses thereafter circulating around its first feedback path until a particular pulse coincides with a sampling pulse at said second gate, each of these pulses also passing into the first register of said first Deltic correlator and then, at the time of occurrence of the next sampling pulse, through the first gate of said second Deltic correlator into the first delay line of said second Deltic correlator and thereafter circulating around its first feedback until a particular pulse coincides with the appearance of a sampling pulse at the first gate of said second Deltic correlator, said pulses being time compressed because of the length of the delay lines compared to the time interval between sampling pulses whereby complementary time compressed input signal pulse trains representing adjacent portions of said input signal appear in the output of the first delay lines of said Deltic correlators; means for connecting a reference signal to the third gate of said first Deltic correlator; means for connecting the output of the second 1-bit register of said first Deltic correlator to the first gate of said second Deltic correlator; means for additionally controlling the operation of the third, fourth and fifth gates and said second 1-bit registers such that either a first mode of operation is obtained wherein the time compressed reference signal pulse trains which appear in the output of the second delay of said Deltic correlators represent the same adjacent portions of said reference signal or a second mode of operation is obtained wherein these signal pulse trains represent changing adjacent portions of said reference signal, each Deltic correlator also having means for multiplying the time compressed pulse trains appearing in the output of its first and second delay lines and for integrating the results thereof to obtain an output signal whose amplitude is indicative of the correlation between those portions of the input and reference signal which are represented by these pulse trains; and means for combining the output signals from each Deltic correlator to give an overall output signal for the cascaded system.