Predicted iteration in decimal division

Claim 2

A divide apparatus, comprising: arithmetic means for performing division; means to compare a divisor and a dividend; and means responsive to said last named means to cause said arithmetic means to perform a restoring type divide iteration or a nonrestoring type divide iteration, alternatively.

Claim 3

The device described in claim 1, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iteration, alternatively, interspersed with operation of said shift means.

Claim 4

In a data processing system, a divide apparatus, comprising: a pair of registers for holding a dividend and a divisor; comparing means responsive to said registers for comparing the dividend and the divisor; arithmetic means responsive to said registers for performing arithmetic operations on the contents thereof, said arithmetic means capable, in response to particular control, to restore a true or complement dividend to its previous complement or true form or to retain said dividend in its true or complement form, alternatively; and means responsive to said comparing means for supplying said particular control to said arithmetic means.

Claim 5

In a data processing system, a divide apparatus, comprising: a pair of registers for holding a dividend and a divisor; comparing means responsive to said registers for comparing the dividend and the divisor; arithmetic means responsive to said registers for performing arithmetic operations on the contents thereof, said arithmetic means capable, in response to particular control, to restore a true or complement dividend to its previous complement or true form or to retain said dividend in its true or complement form, alternatively; and means responsive to said comparing means for supplying said particular control to said arithmetic means.

Claim 6

A decimal divider, comprising: arithmetic means for performing restoring type divide iterations and for performing nonrestoring type divide iterations; and means for selecting between the restoring and nonrestoring iterations of said arithmetic means.

Claim 7

A decimal divider, comprising: arithmetic means for performing restoring type divide iterations and for performing nonrestoring type divide iterations; and means for selecting between the restoring and nonrestoring iterations of said arithmetic means.

Claim 8

The device described in claim 4, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.

Claim 9

A divide apparatus, comprising: arithmetic means for performing division; means to compare the first digit of a divisor and the first digit of a dividend; and means responsive to said last named means to cause said arithmetic means to perform a restoring type divide iteration or a nonrestoring type divide iteration, alternatively.

Claim 10

A divide apparatus, comprising: arithmetic means for performing division; means to compare the first digit of a divisor and the first digit of a dividend; and means responsive to said last named means to cause said arithmetic means to perform a restoring type divide iteration or a nonrestoring type divide iteration, alternatively.

Claim 11

The device described in claim 6, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.

Claim 12

In a data processing system, a divide apparatus, comprising: a pair of registers for holding a dividend and a divisor; comparing means responsive to said registers for comparing the first digit of a dividend and the first digit of a divisor; arithmetic means responsive to said registers for performing arithmetic operations on the contents thereof, said arithmetic means capable, in response to particular control, to perform restoring type divide iterations or nonrestoring type divide iterations, alternatively; and means responsive to said comparing means for supplying said particular control to said arithmetic means.

Claim 13

In a data processing system, a divide apparatus, comprising: a pair of registers for holding a dividend and a divisor; comparing means responsive to said registers for comparing the first digit of a dividend and the first digit of a divisor; arithmetic means responsive to said registers for performing arithmetic operations on the contents thereof, said arithmetic means capable, in response to particular control, to perform restoring type divide iterations or nonrestoring type divide iterations, alternatively; and means responsive to said comparing means for supplying said particular control to said arithmetic means.

Claim 14

The device described in claim 8, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.

Claim 15

A decimal divider, comprising: arithmetic means for performing restoring type divide iterations and nonrestoring-type divide iterations; means for comparing the first digits of the divisor and dividend; and means responsive to said last named means for selecting between the restoring and nonrestoring iterations of said arithmetic means.

Claim 16

A decimal divider, comprising: arithmetic means for performing restoring type divide iterations and nonrestoring-type divide iterations; means for comparing the first digits of the divisor and dividend; and means responsive to said last named means for selecting between the restoring and nonrestoring iterations of said arithmetic means.

Claim 17

The device described in claim 10, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.

Claim 18

A divide apparatus comprising: register means for holding a divisor and a dividend; comparing means for comparing said divisor and dividend; arithmetic means operatively connected to said register means for performing arithmetic operations on the contents thereof, said arithmetic means capable of performing restoring type divide iterations or nonrestoring-type divide iterations, alternatively; indicating means for manifesting a signal indicative of the true or complement form of a dividend; and control means having an output operatively connected to said arithmetic means and inputs operatively connected to said comparing means and said indicating means; said control means being responsive to at least a first predetermined combination of signals from said comparing means and said indicating means to cause said arithmetic means to perform a restoring type of divide iteration; said control means also being responsive to at least a second predetermined combination of signals from said comparing means and said indicating means to cause said arithmetic means to perform a nonrestorIng type of divide iteration.

Claim 19

A divide apparatus comprising: register means for holding a divisor and a dividend; comparing means for comparing said divisor and dividend; arithmetic means operatively connected to said register means for performing arithmetic operations on the contents thereof, said arithmetic means capable of performing restoring type divide iterations or nonrestoring-type divide iterations, alternatively; indicating means for manifesting a signal indicative of the true or complement form of a dividend; and control means having an output operatively connected to said arithmetic means and inputs operatively connected to said comparing means and said indicating means; said control means being responsive to at least a first predetermined combination of signals from said comparing means and said indicating means to cause said arithmetic means to perform a restoring type of divide iteration; said control means also being responsive to at least a second predetermined combination of signals from said comparing means and said indicating means to cause said arithmetic means to perform a nonrestorIng type of divide iteration.