Apparatus for transferring data from a plurality of low-speed devices to a high-speed processor

Claim 2

Apparatus for transferring data between a plurality of lowspeed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; switching means, said switching means being connected between said register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said register, said timing means being connected to said register, said timing means causing said register to sequentially store data from each of said devices; a data register, said data register being connected between said shift register and said processor; and a counter, said counter being coupled to said shift register, said counter counting the number of bits of data received from each of said devices, said counter storing the bit count in said shift register and said delay line.

Claim 3

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 1 wherein: said counter and said timing means cause said switching means to sample each bit of data substantially at the center of the bit of data.

Claim 4

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 1 including: means for transferring data from said shift register to said data register when a complete character has been stored in said shift register and in said delay line, said means causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected to said data register and to said shift register.

Claim 5

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 1 wherein: said counter and said timing means causing said switching means to sample each bit of data substantially at the center of the bit of data; and means for transferring data from said shift register to said data register when a complete character has been stored in said shift register and in said delay line, said means causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected to said data register and to said shift register.

Claim 6

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; switching means, said switching means being connected between said register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said register, said timing means being connected to said register, said timing means causing said register to sequentially store data from each of said devices; a data register, said data register being connected between said shift register and said processor; and means for transferring data from said shift register to said data register when a complete character has been stored in said shift register and in said delay line, said means causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected to said data register and to said shift register.

Claim 7

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; switching means, said switching means being connected between said register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said register, said timing means being connected to said register, said timing means causing said register to sequentially store data from each of said devices; a data register, said data register being connected between said shift register and said processor; and means for transferring data from said shift register to said data register when a complete character has been stored in said shift register and in said delay line, said means causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected to said data register and to said shift register.

Claim 8

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means, switching means, said switching means being connected between said register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said register, said timing means being connected to said register, said timing means causing saiD register to sequentially store data from each of said devices; and a data register, said data register being connected between said shift register and said processor; and a channel register, said channel register being connected between said processor and said timing means, said channel register being used to store the identity of the device which provided the data stored in said data register.

Claim 9

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means, switching means, said switching means being connected between said register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said register, said timing means being connected to said register, said timing means causing saiD register to sequentially store data from each of said devices; and a data register, said data register being connected between said shift register and said processor; and a channel register, said channel register being connected between said processor and said timing means, said channel register being used to store the identity of the device which provided the data stored in said data register.

Claim 10

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 14 including: first and second channel registers, said first channel register being connected between said timing means and said processor, said second channel register being connected between said timing means and said data processor, said second channel register being coupled to said shift register.

Claim 11

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; switching means, said switching means being connected between said shift register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said shift register, said timing means being connected to said shift register, said timing means causing said shift register to sequentially store data from each of said devices; a data register, said data register being connected between said shift register and said processor; a channel register, said channel register being connected between said processor and said timing means, said channel register being used to store the identity of the device which provided the data stored in said data register; a counter, said counter being coupled to said shift register, said counter counting the number of bits of data received from each of said devices, said counter storing the bit count in said shift register and in said delay line; and means for transferring data from said shift register to said data register when a complete character has been stored in said shift register and in said delay line, said means for transferring causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected to said data register and to said shift register.

Claim 12

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; switching means, said switching means being connected between said shift register and each of said devices, said timing means being connected to said switching means, said timing means causing said switching means to sequentially connect each of said devices to said shift register, said timing means being connected to said shift register, said timing means causing said shift register to sequentially store data from each of said devices; a data register, said data register being connected between said shift register and said processor; a channel register, said channel register being connected between said processor and said timing means, said channel register being used to store the identity of the device which provided the data stored in said data register; a counter, said counter being coupled to said shift register, said counter counting the number of bits of data received from each of said devices, said counter storing the bit count in said shift register and in said delay line; and means for transferring data from said shift register to said data register when a complete character has been stored in said shift register and in said delay line, said means for transferring causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected to said data register and to said shift register.

Claim 13

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; first and second switching means, said first switching means being connected between said shift register and each of a plurality of input devices, said second switching means being connected between said shift register and each of a plurality of output devices, said timing means causing said first switching means to sequentially connect each of said input devices to said shift register, said timing means causing said second switching means to sequentially connect each of said output devices to said shift register, said timing means being connected to said shift register, said timing means causing said shift register to sequentially store data from each of said input devices and to transfer data sequentially to each of said output devices; first and second data registers, each of said data registers being connected between said shift register and said data processor.

Claim 14

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: a delay line; a shift register, said register being connected between a first end and a second end of said delay line; timing means; first and second switching means, said first switching means being connected between said shift register and each of a plurality of input devices, said second switching means being connected between said shift register and each of a plurality of output devices, said timing means causing said first switching means to sequentially connect each of said input devices to said shift register, said timing means causing said second switching means to sequentially connect each of said output devices to said shift register, said timing means being connected to said shift register, said timing means causing said shift register to sequentially store data from each of said input devices and to transfer data sequentially to each of said output devices; first and second data registers, each of said data registers being connected between said shift register and said data processor.

Claim 15

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 8 including: a counter, said counter being coupled to said shift register, said counter counting the number of bits of data received from each of said input devices and storing the bit count of said data received in said shift register and said delay line, said counter counting the number of bits of data transferred from said shift register to each of said output devices, said counter storing the bit count of said data transferred in said shift register and in said delay line.

Claim 16

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 8 including: a counter, said counter being coupled to said shift register, said counter coUnting the number of bits of data received from each of said input devices and storing the bit count of said data received in said shift register and said delay line, said counter counting the number of bits of data transferred from said shift register to each of said output devices, said counter storing the bit count of said data transferred in said shift register and in said delay line, said counter and said timing means causing said switching means to sample each bit of data substantially at the center of the bit of data.

Claim 17

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 8 including: first and second channel registers, each of said channel registers being connected between said shift register and said processor.

Claim 18

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 8 including: means for transferring data from said shift register to said first data register when a complete character has been stored in said shift register and in said delay line, said means causing all of the bits of a complete character to be transferred simultaneously from said shift register to said data register, said means for transferring being connected between said first data register and said shift register; and means for transferring data from said second data register to said shift register, said means for transferring said data from said second data register to said shift register being connected between said processor and said shift register.

Claim 19

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: first and second shift registers; first and second delay lines, each of said shift registers being connected between a first end and a second end of a corresponding one of said delay lines; timing means; first and second switching means, said first switching means being connected between said first register and each of a plurality of input devices, said second switching means being connected between said second shift register and each of a plurality of output devices, said timing means being connected to said first and to said second switching means, said timing means causing said first switching means to sequentially connect each of said input devices to said first shift register, said timing means causing said second switching means to sequentially connect each of said output devices to said second shift register, said timing means being connected to said first and to second shift registers, said timing means causing said first shift register to sequentially store data from each of said input devices, said timing means causing data to be sequentially transferred from said second shift register to each of said output devices; and first and second data registers, said first data register being connected between said first shift register and said processor, said second data register being connected between said second shift register and said processor.

Claim 20

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor comprising: first and second shift registers; first and second delay lines, each of said shift registers being connected between a first end and a second end of a corresponding one of said delay lines; timing means; first and second switching means, said first switching means being connected between said first register and each of a plurality of input devices, said second switching means being connected between said second shift register and each of a plurality of output devices, said timing means being connected to said first and to said second switching means, said timing means causing said first switching means to sequentially connect each of said input devices to said first shift register, said timing means causing said second switching means to sequentially connect each of said output devices to said second shift register, said timing means being connected to said first and to second shift registers, said timing means causing said first shift register to sequentially store data from each of said input devices, said timing means causing data to be sequentially transferred from said second shift register to each of said output devices; and first and second data registers, said first data register being connected between said first shift register and said processor, said second data register being connected between said second shift register and said processor.

Claim 21

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 13 including: first and second counters, said first counter being coupled to said first shift register, said first counter counting the number of bits of data received from each of said input devices, said counter storing the bit count in said shift register and said first delay line, said second counter being coupled to said second shift register, said second counter counting the number of bits of data transferred from said second shift register to each of said output devices, said second counter storing the bit count in said second shift register and in said second delay line.

Claim 22

Apparatus for transferring data between a plurality of low-speed devices and a high-speed data processor as defined in claim 13 including: first and second counters, said first counter being coupled to said first shift register, said first counter counting the number of bits of data received from each of said input devices, said counter storing the bit count in said shift register and said first delay line, said first counter and said timing means causing said switching means to sample each bit of data substantially at the center of the bit of data, said second counter being coupled to said second shift register, said second counter counting the number of bits of data transferred from said second shift register to each of said output devices, said second counter storing the bit count in said second shift register and in said second delay line.