US3586987A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor bias circuit
Assignee: Fairchild Semiconductor Corp
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Filing: 1969-04-10
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Granted: 1971-06-22
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Expires: 1989-04-10
Abstract
Abstract A circuit for biasing transistors particularly suited for monolithic circuits utilizes a pair of NPN-PNP input transistors operating in conjunction with a constant-current source. The biasing circuit enables the input bias current to be substantially independent of the current gain of the PNP transistors.
Inventors
- 👤 David J Fullagar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:40
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45479
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
232 words
In an amplifier input stage comprising: a first and second transistor each having at least a collector, a base and an emitter electrode, each of said base electrode suitable for receiving an input signal; third and fourth transistors each having an emitter, a base and a collector electrode, the base electrode of said third transistor coupled to the base electrode of said fourth transistor to form a common-base connection; said emitter electrode of said first transistor coupled to the emitter electrode of said third transistor and the emitter electrode of said second transistor coupled to the emitter electrode of said fourth transistor; said collector electrodes of said third and fourth transistors each coupled to a load, said common-base connection coupled to a source of constant current; and a biasing circuit for providing a potential for the input stage comprising: a fifth transistor having at least an emitter, a base and a collector electrode, said emitter electrode coupled to a source of direct-current potential, said base electrode coupled to said collector electrode, said collector electrode coupled to the collector electrodes of Said first and second transistors; and a sixth transistor having at least an emitter, a base and a collector electrode, said emitter electrode coupled to said source of direct-current potential, said base electrode coupled to the base electrode of said fifth transistor, said collector electrode coupled to said source of constant current.
Claim 2
Dependent Claim
32 words
The circuit defined in claim 2 wherein said first and second transistors of said input stage are NPN transistors and said third and fourth transistors of said input stage are PNP transistors.
Claim 3
Dependent Claim
19 words
The circuit defined in claim 3 wherein said fifth and sixth transistors comprising said biasing circuit are PNP transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |