US3586982A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse count detector having fail-safe features
Assignee: Westinghouse Electric Corp
•
Filing: 1969-02-19
•
Granted: 1971-06-22
•
Expires: 1989-02-19
Abstract
Abstract A flip-flop digital counter is reset periodically by a reset pulse, and upcounted by count pulses. A network is connected to the individual flip-flop outputs to sense presence of a predetermined count condition in the counter together with dynamic behavior of the individual flip-flops. Another network is connected to the individual flip-flops and to the input connection to the reset line to detect simultaneous resetting to zero condition of each flip-flop with appearance of a reset pulse. The output of these two networks is passed to another network with checks for presence of both the count condition and such reset in each count cycle.
Inventors
- 👤 Robert C Hoyler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:25
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; B; B60; B60L; B60L2200/00; B60L2200/26
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
172 words
In a count condition responsive circuit, the combination comprising: counter means comprising a plurality of bistable elements and including a count signal input and a reset signal input, said counter means being reset to a zero binary state in response to a reset signal and to count up in response to a count signal; first means for providing an output signal in response to a predetermined count condition in the counter means; second means responsive to each of the bistable elements being concurrently reset for validating said output signal; said first and second means each comprising a series of enable gate circuits cascade connected to form an enable signal channel, with one enable gate circuit being connected to each bistable element, with each enable gate circuit including a binary signal state sensing circuit operative to actuate the enable gate circuit to a signal passing condition in response to the bistable element to which it is connected producing a predetermined binary signal state at a frequency in excess of a predetermined minimum frequency.
Claim 2
Dependent Claim
172 words
In a count condition responsive circuit, the combination comprising: counter means comprising a plurality of bistable elements and including a count signal input and a reset signal input, said counter means being reset to a zero binary state in response to a reset signal and to count up in response to a count signal; first means for providing an output signal in response to a predetermined count condition in the counter means; second means responsive to each of the bistable elements being concurrently reset for validating said output signal; said first and second means each comprising a series of enable gate circuits cascade connected to form an enable signal channel, with one enable gate circuit being connected to each bistable element, with each enable gate circuit including a binary signal state sensing circuit operative to actuate the enable gate circuit to a signal passing condition in response to the bistable element to which it is connected producing a predetermined binary signal state at a frequency in excess of a predetermined minimum frequency.
Claim 3
Dependent Claim
111 words
In combination: an n stage counter, where n is an integer, which counts in response to count pulses; first means responsive to a predetermined count from said counter concurrent with the application of an input signal to said first means for producing a first signal; second means responsive to said counter being reset for producing a second signal; third means responsive to said second signal for producing a third signal having a time duration at least as long as the time duration needed for said counter to count to said predetermined count; and fourth means responsive to the concurrent production of said first and third signals for producing an output signal.
Claim 4
Dependent Claim
111 words
In combination: an n stage counter, where n is an integer, which counts in response to count pulses; first means responsive to a predetermined count from said counter concurrent with the application of an input signal to said first means for producing a first signal; second means responsive to said counter being reset for producing a second signal; third means responsive to said second signal for producing a third signal having a time duration at least as long as the time duration needed for said counter to count to said predetermined count; and fourth means responsive to the concurrent production of said first and third signals for producing an output signal.
Claim 5
Dependent Claim
126 words
In combination: an n stage counter, where n is an integer, which counts in response to count pulses; first means responsive to a predetermined count from said counter concurrent with the application of an input signal to said first means for producing a first signal; second means responsive to said counter being reset concurrent with the application of said input signal to said second means for producing a second signal; third means responsive to said second signal for producing a third signal of a time duration at least as long as the time duration needed for said counter to count to said predetermined count after being reset; and fourth means responsive to the concurrent production of said first and third signals for producing an output signal.
Claim 6
Dependent Claim
126 words
In combination: an n stage counter, where n is an integer, which counts in response to count pulses; first means responsive to a predetermined count from said counter concurrent with the application of an input signal to said first means for producing a first signal; second means responsive to said counter being reset concurrent with the application of said input signal to said second means for producing a second signal; third means responsive to said second signal for producing a third signal of a time duration at least as long as the time duration needed for said counter to count to said predetermined count after being reset; and fourth means responsive to the concurrent production of said first and third signals for producing an output signal.
Claim 7
Dependent Claim
164 words
In combination: first means for generating a periodic signal; an n stage counter, where n is an integer, which counts in response to input pulses; second means having an input to which said periodic signal may be applied, and an output where said periodic signal is reproduced in response to a predetermined count from said counter; third means having an input to which said periodic signals may be applied, and an output where said periodic signal is reproduced in response to said counter being reset; and fourth means responsive to said periodic signal being reproduced at the output of said third means for producing a pulse having a time duration at least as long as the time duration needed for said counter to count to said predetermined count after being reset; and fifth means responsive to said periodic signal being reproduced at the outPut of said second means concurrent with the production of said pulse by said fourth means for reproducing said periodic signal.
Claim 8
Dependent Claim
164 words
In combination: first means for generating a periodic signal; an n stage counter, where n is an integer, which counts in response to input pulses; second means having an input to which said periodic signal may be applied, and an output where said periodic signal is reproduced in response to a predetermined count from said counter; third means having an input to which said periodic signals may be applied, and an output where said periodic signal is reproduced in response to said counter being reset; and fourth means responsive to said periodic signal being reproduced at the output of said third means for producing a pulse having a time duration at least as long as the time duration needed for said counter to count to said predetermined count after being reset; and fifth means responsive to said periodic signal being reproduced at the outPut of said second means concurrent with the production of said pulse by said fourth means for reproducing said periodic signal.
Claim 9
Dependent Claim
12 words
The combination claimed in claim 4 said fourth means comprising an integrator.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |