High voltage ceramic capacitor assembly and method of making same

Claim 3

The method of claim 1 in which said machining operation is an abrading operation.

Claim 4

The method of claim 1 in which said machining operation is a grinding operation performed on a work-rotating machine tool.

Claim 5

A method as defined in claim 1 and further comprising: a. bonding to each of the conductive coatings at the outer ends of said stack an end block of electrical insulating material having a surface abutting said coating about substantially the entire outer perIpheral region of said coating, b. then machining the periphery of each of said end blocks, said juxtaposed conductive coating, and the adjacent ceramic block sufficiently to achieve in the region of said coating precise alignment between the outer peripheral surfaces of said coating and said adjacent ceramic block about the entire peripheral surface of said coating.

Claim 8

A high voltage ceramic capacitor assembly comprising: a. a stack of ceramic capacitor blocks electrically connected in series, each having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely thereof, and a conductive coating bonded to each of said planar faces, b. one of the conductive coatings on each capacitor block having a face in juxtaposition to a face of one of the coatings on an immediately-adjacent capacitor block, c. bonding means providing an adherent bond between said juxtaposed coatings securing said ceramic blocks together with the peripheral surfaces of adjacent ceramic blocks in precisely-aligned relationship, d. each of said ceramic blocks having a substantially chip-free peripheral surface immediately adjacent the conductive coatings thereon, e. each of said conductive coatings having a chip-free peripheral edge extending about the entire outer periphery of said stack in precisely-aligned relationship with the peripheral surface of the ceramic capacitor material there adjacent, f. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic blocks adjacent said conductive coating, the juxtaposed faces of each of said conductive coatings between said ceramic capacitor blocks being free of insulating coating of a thickness greater than 15 mils, g. the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks being less than 5 mils, h. said juxtaposed conductive coatings being less than 15 mils apart and so close together as to substantially prevent the presence of lines of electric flux emanating from the region between said juxtaposed coatings and crowding around the peripheral edge of a conductive coating as they enter the ceramic when a high voltage is applied between the ends of said stack.

Claim 9

A high voltage ceramic capacitor assembly comprising: a. a stack of ceramic capacitor blocks electrically connected in series, each having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely thereof, and a conductive coating bonded to each of said planar faces, b. one of the conductive coatings on each capacitor block having a face in juxtaposition to a face of one of the coatings on an immediately-adjacent capacitor block, c. bonding means providing an adherent bond between said juxtaposed coatings securing said ceramic blocks together with the peripheral surfaces of adjacent ceramic blocks in precisely-aligned relationship, d. each of said ceramic blocks having a substantially chip-free peripheral surface immediately adjacent the conductive coatings thereon, e. each of said conductive coatings having a chip-free peripheral edge extending about the entire outer periphery of said stack in precisely-aligned relationship with the peripheral surface of the ceramic capacitor material there adjacent, f. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic blocks adjacent said conductive coating, the juxtaposed faces of each of said conductive coatings between said ceramic capacitor blocks being free of insulating coating of a thickness greater than 15 mils, g. the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks being less than 5 mils, h. said juxtaposed conductive coatings being less than 15 mils apart and so close together as to substantially prevent the presence of lines of electric flux emanating from the region between said juxtaposed coatings and crowding around the peripheral edge of a conductive coating as they enter the ceramic when a high voltage is applied between the ends of said stack.

Claim 10

The high voltage ceramic capacitor assembly of claim 6 in which the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks is less than 2 mils.

Claim 11

The high voltage ceramic capacitor assembly of claim 6 in which the periphery of said stack, considered without said dielectric coating, has a surface smoothness in the region of each of said conductive coatings corresponding to that resulting from grinding smooth said peripheral surface regions on a work-rotating grinding machine.

Claim 12

The high voltage ceramic capacitor assembly of claim 6 in which the space between the juxtaposed substantially planar faces of adjacent capacitor blocks is less than 15 mils.

Claim 13

The high volTage capacitor assembly of claim 6 in which the space between the juxtaposed substantially planar faces of adjacent ceramic capacitor blocks is less than 5 mils.

Claim 14

A high voltage ceramic capacitor assembly comprising: a. a stack of ceramic capacitor blocks electrically connected in series, each having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely thereof, and a conductive coating bonded to each of said planar faces, b. one of the conductive coatings on each capacitor block being in juxtaposed position to one of the coatings on an immediately-adjacent capacitor block, c. bonding means providing an adherent bond between said juxtaposed coatings securing said ceramic blocks together with the peripheral surfaces of adjacent ceramic blocks in precisely-aligned relationship, d. each of said ceramic blocks having a substantially chip-free peripheral surface immediately adjacent the conductive coatings thereon, e. each of said conductive coatings having a substantially chip-free peripheral edge extending about the entire outer periphery of said stack in precisely aligned relationship with the peripheral surface of the ceramic capacitor material there adjacent, f. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic blocks adjacent said conductive coating, g. the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks being less than 5 mils, h. said juxtaposed conductive coatings being so close together as to substantially prevent the presence of lines of electric flux emanating from the region between said juxtaposed coatings and crowding around the peripheral edge of a conductive coating as they enter the ceramic when a high voltage is applied between the ends of said stack, i. a pair of end blocks of electrical insulating material at opposite ends of said stack, each having a surface bonded to one of the conductive coatings at the outer end of said stack and abutting said outer end coating about substantially the entire outer peripheral region of said coating, j. the periphery of each of said outer end coatings being substantially free of chips and having a peripheral edge extending about the entire periphery of said stack in precisely-aligned relationship with the peripheral surface of the ceramic capacitor material and the end block material there adjacent.

Claim 15

A high voltage ceramic capacitor assembly comprising: a. a stack of ceramic capacitor blocks electrically connected in series, each having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely thereof, and a conductive coating bonded to each of said planar faces, b. one of the conductive coatings on each capacitor block being in juxtaposed position to one of the coatings on an immediately-adjacent capacitor block, c. bonding means providing an adherent bond between said juxtaposed coatings securing said ceramic blocks together with the peripheral surfaces of adjacent ceramic blocks in precisely-aligned relationship, d. each of said ceramic blocks having a substantially chip-free peripheral surface immediately adjacent the conductive coatings thereon, e. each of said conductive coatings having a substantially chip-free peripheral edge extending about the entire outer periphery of said stack in precisely aligned relationship with the peripheral surface of the ceramic capacitor material there adjacent, f. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic blocks adjacent said conductive coating, g. the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks being less than 5 mils, h. said juxtaposed conductive coatings being so close together as to substantially prevent the presence of lines of electric flux emanating from the region between said juxtaposed coatings and crowding around the peripheral edge of a conductive coating as they enter the ceramic when a high voltage is applied between the ends of said stack, i. a pair of end blocks of electrical insulating material at opposite ends of said stack, each having a surface bonded to one of the conductive coatings at the outer end of said stack and abutting said outer end coating about substantially the entire outer peripheral region of said coating, j. the periphery of each of said outer end coatings being substantially free of chips and having a peripheral edge extending about the entire periphery of said stack in precisely-aligned relationship with the peripheral surface of the ceramic capacitor material and the end block material there adjacent.

Claim 16

A high voltage ceramic capacitor unit comprising: a. a ceramic capacitor block having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely of said peripheral surface, and a conductive coating bonded to each of said planar faces, b. a pair of end blocks of electrical insulating material, each having a surface bonded to one of the conductive coatings on said ceramic block and abutting said coating about substantially the entire outer peripheral region of said coating, c. said ceramic block and said end blocks together forming a stack, d. the periphery of each of said conductive coatings being substantially free of chips and having a peripheral edge extending about the entire periphery of said stack in precisely-aligned relationship with the peripheral surface of the ceramic capacitor material and the end block material there adjacent, e. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic block adjacent said conductive coating.

Claim 17

A high voltage ceramic capacitor unit comprising: a. a ceramic capacitor block having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely of said peripheral surface, and a conductive coating bonded to each of said planar faces, b. a pair of end blocks of electrical insulating material, each having a surface bonded to one of the conductive coatings on said ceramic block and abutting said coating about substantially the entire outer peripheral region of said coating, c. said ceramic block and said end blocks together forming a stack, d. the periphery of each of said conductive coatings being substantially free of chips and having a peripheral edge extending about the entire periphery of said stack in precisely-aligned relationship with the peripheral surface of the ceramic capacitor material and the end block material there adjacent, e. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic block adjacent said conductive coating.

Claim 18

A high voltage capacitor assembly comprising a plurality of series-connected capacitor units each constructed as defined in claim 12, said capacitor units being disposed in stacked relationship with conductive buttons located between adjacent capacitor units and contacting the conductive coaTings thereon, said end blocks of insulating material that are located between said ceramic blocks being of annular form so as to leave a central portion of the associated conductive coatings bare to permit contact thereof by the associated button.

Claim 19

A high voltage ceramic capacitor assembly comprising: a. a stack of ceramic capacitor blocks electrically connected in series, each having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely thereof, and a conductive coating bonded to each of said planar faces, b. one of the conductive coatings on each capacitor block being in juxtaposition to one of the coatings on an immediately-adjacent capacitor block, c. bonding means providing an adherent bond between said juxtaposed coatings securing said ceramic blocks together with the peripheral surfaces of adjacent ceramic blocks in precisely-aligned relationship, d. each of said ceramic blocks having a substantially chip-free peripheral surface immediately adjacent the conductive coatings, thereon, e. each of said conductive coatings having a substantially chip-free periphery of said stack in precisely aligned relationship with the peripheral surface of the ceramic capacitor material there adjacent, f. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic blocks adjacent said conductive coating, g. the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks being less than 5 mils, h. said juxtaposed conductive coatings being so close together as to substantially prevent the presence of lines of electric flux emanating from the region between said juxtaposed coatings and crowding around the peripheral edge of a conductive coating as they enter the ceramic when a high voltage is applied between the ends of said stack, and i. end terminals respectively contacting the conductive coatings at the ends of said stack, said end terminals and all other conductive structure immediately adjacent the conductive coatings at the ends of said stack being located radially inwardly of the outer peripheries of said end conductive coatings.

Claim 20

A high voltage ceramic capacitor assembly comprising: a. a stack of ceramic capacitor blocks electrically connected in series, each having an outer peripheral surface, a pair of opposed substantially planar faces extending transversely thereof, and a conductive coating bonded to each of said planar faces, b. one of the conductive coatings on each capacitor block being in juxtaposition to one of the coatings on an immediately-adjacent capacitor block, c. bonding means providing an adherent bond between said juxtaposed coatings securing said ceramic blocks together with the peripheral surfaces of adjacent ceramic blocks in precisely-aligned relationship, d. each of said ceramic blocks having a substantially chip-free peripheral surface immediately adjacent the conductive coatings, thereon, e. each of said conductive coatings having a substantially chip-free periphery of said stack in precisely aligned relationship with the peripheral surface of the ceramic capacitor material there adjacent, f. a thin coating of insulating material covering the peripheral edge of each of said conductive coatings and the immediately adjacent peripheral surface of the ceramic blocks adjacent said conductive coating, g. the maximum misalignment between the peripheral edge of all of the conductive coatings and the adjacent peripheral surface of the ceramic capacitor blocks being less than 5 mils, h. said juxtaposed conductive coatings being so close together as to substantially prevent the presence of lines of electric flux emanating from the region between said juxtaposed coatings and crowding around the peripheral edge of a conductive coating as they enter the ceramic when a high voltage is applied between the ends of said stack, and i. end terminals respectively contacting the conductive coatings at the ends of said stack, said end terminals and all other conductive structure immediately adjacent the conductive coatings at the ends of said stack being located radially inwardly of the outer peripheries of said end conductive coatings.

Claim 21

The method of claim 4 in which machining of the periphery of each end block, juxtaposed conductive coating bonded thereto, and adjacent ceramic block produces in the region of said coating precise-alignment between the outer peripheral surfaces of said end block, said coating, and said adjacent ceramic block about the entire peripheral surface of said coating.

Claim 22

The method of claim 5 in which machining of the periphery of each end block, juxtaposed conductive coating bonded thereto, and adjacent ceramic block produces in the region of said coating precise-alignment between the outer peripheral surfaces of said end block, said coating, and said adjacent ceramic block about the entire peripheral surface of said coating.