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US3586887A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tetrode fet noise figure by neutralization and tuning
Assignee: University of Minnesota Twin Cities
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Filing: 1969-01-03
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Granted: 1971-06-22
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Expires: 1989-01-03
Abstract
Abstract A tetrode field effect transistor capable of having an improved noise figure is shown. Circuitry is shown for neutralizing the drain-to-gate capacitance of the first half of the tetrode near cutoff frequency, and circuitry is also shown for tuning the interstage network between the first and second half of the tetrode field effect transistor.
Inventors
- 👤 Aldert Van Der Ziel
- 👤 Keiji Takagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:37
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F3/1935
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
122 words
An improved field effect transistor circuit comprising first half-circuit and second half-circuit means arranged on tetrode field effect semiconductor translating means disposed on a common semiconductor substrate, said first half-circuit means having a first source terminal means, a first gate terminal means, and a first drain means; said second half-circuit means having second source means coupled directly to and in common with said first drain means, second gate terminal means, and second drain terminal means; tuning terminal means coupled to said common first drain means second source means; and interstage tuning means coupled to said tuning terminal means anD said second halfcircuit means for tuning said first half-circuit means to said second half-circuit means for improving the noise figure of said circuit.
Claim 2
Dependent Claim
122 words
An improved field effect transistor circuit comprising first half-circuit and second half-circuit means arranged on tetrode field effect semiconductor translating means disposed on a common semiconductor substrate, said first half-circuit means having a first source terminal means, a first gate terminal means, and a first drain means; said second half-circuit means having second source means coupled directly to and in common with said first drain means, second gate terminal means, and second drain terminal means; tuning terminal means coupled to said common first drain means second source means; and interstage tuning means coupled to said tuning terminal means anD said second halfcircuit means for tuning said first half-circuit means to said second half-circuit means for improving the noise figure of said circuit.
Claim 3
Dependent Claim
18 words
A circuit as in claim 1 wherein said first and second half-circuit means comprise a cascode circuit arrangement.
Claim 4
Dependent Claim
129 words
An improved field effect transistor circuit comprising first half-circuit and second half-circuit means arranged on tetrode field effect semiconductor translating means disposed on a common semiconductor substrate, said first half-circuit means having a first source terminal means, a first gate terminal means, and a first drain means; said second half-circuit means having second source means coupled directly to and in common with said first drain means, second gate terminal means, and second drain terminal means; tuning terminal means coupled to said common first drain means and second source means; and capacitance neutralization means coupled to said tuning terminal means and said first half-circuit means for neutralizing the effects of capacitance between said first gate terminal means and said first drain means for improving the noise figure of said circuit.
Claim 5
Dependent Claim
129 words
An improved field effect transistor circuit comprising first half-circuit and second half-circuit means arranged on tetrode field effect semiconductor translating means disposed on a common semiconductor substrate, said first half-circuit means having a first source terminal means, a first gate terminal means, and a first drain means; said second half-circuit means having second source means coupled directly to and in common with said first drain means, second gate terminal means, and second drain terminal means; tuning terminal means coupled to said common first drain means and second source means; and capacitance neutralization means coupled to said tuning terminal means and said first half-circuit means for neutralizing the effects of capacitance between said first gate terminal means and said first drain means for improving the noise figure of said circuit.
Claim 6
Dependent Claim
44 words
A circuit as in claim 3 and further including interstage tuning means coupled to said tuning terminal means and said second half-circuit means for tuning said first half-circuit means to said second half-circuit means for further improving the noise figure of said circuit .
Claim 7
Dependent Claim
18 words
A circuit as in claim 4 wherein said first and second half-circuit means comprise a cascode circuit arrangement.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |