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US3585487A Expired / Lapsed US ⏱️ 0.0 years remaining

High-speed precision rectifier

Assignee: Unisys Corp
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Filing: 1969-06-26
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Granted: 1971-06-15
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Expires: 1989-06-26
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Abstract

Abstract This invention relates to a high-speed, full-wave rectifier having two parallel forward paths, one for transmitting positive input signals and the other for inverting and transmitting negative input signals to a common output. Each path includes a gate for passing signals in response to a command. A comparator which generates a first voltage in response to a positive input and a second voltage in response to a negative input cooperates with the gates to enable the gate in the first forward path when the input is positive and to enable the gate in the second forward path when the input is negative. Thus, positive signals are passed through the first forward path to the output and negative signals are inverted and passed through the second forward path to the output thereby converting an arbitrary input waveform to full-wave, rectified output waveform.

Inventors

  • 👤 John L Mcnally

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 01:50
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/22; G06; G06G; G06G7/00; G06G7/12; G06G7/25

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 113 words
A full-wave rectifier comprising: an input terminal for receiving an arbitrary signal, an output terminal, first gating means connected to said output terminal, second gating means connected to said output terminal means cooperating with said input terminal for translating said input signal to said first gating means and for inverting and translating said input signal to said second gating means, a source for generating a reference voltage, and means cooperating with said input terminal and said reference source for enabling said first gating means when said input signal is more positive than said reference voltage and for enabling said second gating means when said input signal is more negative than said reference voltage.
Claim 2
Dependent Claim 113 words
A full-wave rectifier comprising: an input terminal for receiving an arbitrary signal, an output terminal, first gating means connected to said output terminal, second gating means connected to said output terminal means cooperating with said input terminal for translating said input signal to said first gating means and for inverting and translating said input signal to said second gating means, a source for generating a reference voltage, and means cooperating with said input terminal and said reference source for enabling said first gating means when said input signal is more positive than said reference voltage and for enabling said second gating means when said input signal is more negative than said reference voltage.
Claim 3
Dependent Claim 64 words
A full-wave rectifier as defined in claim 1 wherein said means cooperating with said input terminal for translating said input signal to said first gating means and for inverting and translating said input signal to said second gating means is a differential amplifier having an in-phase output connected to said first gating means and having an inverted output connected to said second gating means.
Claim 4
Dependent Claim 63 words
A full-wave rectifier as defined In claim 1 wherein said means cooperating with said input terminal for translating said input signal to said first gating means and for inverting and translating said input signal to said second gating means is an amplifier coupling said input terminal with said first gating means and an inverter coupling said input terminal with said second gating means.
Claim 5
Dependent Claim 136 words
A full-wave rectifier as defined in claim 1 wherein said means cooperating with said input terminal and said reference source for enabling one of said gating means when said input signal is more positive than said reference voltage and for enabling the other of said gating means when said input signal is more negative than said reference voltage comprises: a comparator coupled to said input terminal and said reference source, said comparator generating a first voltage when said input signal is more positive than said reference voltage and generating a second voltage when said input voltage is more negative than said reference voltage, first adaption means for enabling one of said gating means in response to said first voltage, and second adaption means for enabling other of said gating means in response to said second voltage.
Claim 6
Dependent Claim 19 words
A full-wave rectifier as defined in claim 1 wherein said first and second gating means are solid-state discharge devices.
Claim 7
Dependent Claim 18 words
A full-wave rectifier as defined in claim 1 wherein said first and second gating means are field-effect transistors.
Claim 8
Dependent Claim 22 words
A full-wave rectifier as defined in claim 1 wherein said first and second gating means each includes means for eliminating switching transients.
Claim 9
Dependent Claim 205 words
A full-wave rectifier comprising: an input terminal for receiving an arbitrary signal, an output terminal, a first differential amplifier having an output connected with said output terminal, a second differential amplifier having an output connected with said output terminal, a first pair of gating means each connected to an individual input of said first differential amplifier, a second pair of gating means each connected to an individual input of said second differential amplifier, first means cooperating with said input terminal for translating said input signal to one of said first pair of gating means and for inverting and translating said input signal to other of said first pair of gating means, second means cooperating with said input terminal for translating said input signal to one of said second pair of gating means and for inverting and translating said input signal to other of said second pair of gating means, a reference source for generating a reference voltage, means cooperating with said input terminal and said reference source for enabling said first pair of gating means when said input signal is more positive than said reference voltage and for enabling said second pair of gating means when said input is more negative than said reference voltage.
Claim 10
Dependent Claim 205 words
A full-wave rectifier comprising: an input terminal for receiving an arbitrary signal, an output terminal, a first differential amplifier having an output connected with said output terminal, a second differential amplifier having an output connected with said output terminal, a first pair of gating means each connected to an individual input of said first differential amplifier, a second pair of gating means each connected to an individual input of said second differential amplifier, first means cooperating with said input terminal for translating said input signal to one of said first pair of gating means and for inverting and translating said input signal to other of said first pair of gating means, second means cooperating with said input terminal for translating said input signal to one of said second pair of gating means and for inverting and translating said input signal to other of said second pair of gating means, a reference source for generating a reference voltage, means cooperating with said input terminal and said reference source for enabling said first pair of gating means when said input signal is more positive than said reference voltage and for enabling said second pair of gating means when said input is more negative than said reference voltage.
Claim 11
Independent Claim 154 words
A method of full-wave rectifying an arbitrary input signal about a reference voltage comprising the steps of: sensing the polarity of said arbitrary input signal, enabling a first pair of gates when said signal is positive with respect to said reference voltage, enabling a second pair of gates when said signal is negative with respect to said reference voltage, translating the positive portion of said arbitrary signal through said first pair of gates, translating the negative portion of said arbitrary signal through said second pair of gates, cancelling the in-phase portions of said signal translated through said first pair of gates, cancelling the in-phase portions of said signal translated through said second pair of gates, summing the 180* out-of-phase portion of said signal translated through said first pair of gates, summing the 180* out-of-phase portion of said signal translated through said second pair of gages, and feeding the summed signals to an output terminal.
Claim 12
Independent Claim 154 words
A method of full-wave rectifying an arbitrary input signal about a reference voltage comprising the steps of: sensing the polarity of said arbitrary input signal, enabling a first pair of gates when said signal is positive with respect to said reference voltage, enabling a second pair of gates when said signal is negative with respect to said reference voltage, translating the positive portion of said arbitrary signal through said first pair of gates, translating the negative portion of said arbitrary signal through said second pair of gates, cancelling the in-phase portions of said signal translated through said first pair of gates, cancelling the in-phase portions of said signal translated through said second pair of gates, summing the 180* out-of-phase portion of said signal translated through said first pair of gates, summing the 180* out-of-phase portion of said signal translated through said second pair of gages, and feeding the summed signals to an output terminal.

References Cited (Backward Citations)

US3411066A Cited
US3502905A Cited
US3509372A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-06-14 1974-12-14 1975-06-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-06-14 1978-12-14 1979-06-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-06-14 1982-12-14 1983-06-15 $7700.00 Window Closed / Lapsed

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