US3584928A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state display device
Assignee: AT&T Inc
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Filing: 1969-07-01
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Granted: 1971-06-15
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Expires: 1989-07-01
Abstract
Abstract Light emitting p-n junctions are formed by depositing p-type Cu2S along a sample of n-type CdS, the latter having an anode and a cathode and a third terminal adjacent to the cathode. A DC bias voltage is connected in series with a digital-modulating signal and placed across the anode and the cathode of the CdS crystal. A positive trigger pulse, synchronized with the modulating signal, is applied to the third terminal and serves to nucleate an acoustic domain which propagates from cathode to anode. The voltage across the propagating domain is controlled by the digital-modulating signal applied to the device, and as the domain passes under a p-n junction light is emitted by the junction if at that instant the voltage across the domain exceeds a given threshold. Suitable light sensitive storage apparatus may be placed adjacent to each junction thereby permitting rapid storage of the digital signal.
Inventors
- 👤 Richard B Robruck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026; G; G09; G09G; G09G3/00; G11; G11C; G11C13/00; G11C13/04; H10; H10H; H10H20/00; H10H20/80; H10N; H10N80/00; H10N80/10; H10P; H10P95/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
137 words
A solid-state display circuit comprising, in combination, a bulk semiconductor device of n-type semiconductor material having an anode, a cathode, and a third electrode, layers of p-type semiconductor material deposited on a surface of said bulk semiconductor device to form p-n junctions, a source of bias voltage, a source digital modulating voltage, means connecting said source of bias voltage and said source of modulating voltage in series between said anode and cathode, a source of trigger pulses connected to said third electrode so that domains are nucleated in said device, and means to synchronize said modulating voltage to said trigger pulses such that the binary digits of the modulating voltage are associated with the passage of a domain under a p-n junction, whereby each p-n junction emits energy in accordance with the magnitude of the modulating voltage.
Claim 2
Dependent Claim
137 words
A solid-state display circuit comprising, in combination, a bulk semiconductor device of n-type semiconductor material having an anode, a cathode, and a third electrode, layers of p-type semiconductor material deposited on a surface of said bulk semiconductor device to form p-n junctions, a source of bias voltage, a source digital modulating voltage, means connecting said source of bias voltage and said source of modulating voltage in series between said anode and cathode, a source of trigger pulses connected to said third electrode so that domains are nucleated in said device, and means to synchronize said modulating voltage to said trigger pulses such that the binary digits of the modulating voltage are associated with the passage of a domain under a p-n junction, whereby each p-n junction emits energy in accordance with the magnitude of the modulating voltage.
Claim 3
Dependent Claim
150 words
A solid-state display circuit comprising, in combination, a bulk semiconductor device of n-type semiconductor material having an anode, a cathode, and a third electrode, layers of p-type semiconductor material deposited on said bulk semiconductor device to form light emitting p-n junctions, a source of bias voltage, a source of digital modulating signals, means connecting said bias source and said source of digital signals in series between said anode and cathode, a source of trigger pulses connected to said third electrode so that domains are nucleated in said device and means to synchronize said source of digital signals to said trigger pulses such that the binary digits of the modulating signal are associated with domain passage under the p-n junctions, whereby each junction emits energy when a positive pulse is present in the signal from said source of digital signals at the time that a domain passes beneath said p-n junction.
Claim 4
Dependent Claim
150 words
A solid-state display circuit comprising, in combination, a bulk semiconductor device of n-type semiconductor material having an anode, a cathode, and a third electrode, layers of p-type semiconductor material deposited on said bulk semiconductor device to form light emitting p-n junctions, a source of bias voltage, a source of digital modulating signals, means connecting said bias source and said source of digital signals in series between said anode and cathode, a source of trigger pulses connected to said third electrode so that domains are nucleated in said device and means to synchronize said source of digital signals to said trigger pulses such that the binary digits of the modulating signal are associated with domain passage under the p-n junctions, whereby each junction emits energy when a positive pulse is present in the signal from said source of digital signals at the time that a domain passes beneath said p-n junction.
References Cited (Backward Citations)
US3447044A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-14 | 1974-12-14 | 1975-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-14 | 1978-12-14 | 1979-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-14 | 1982-12-14 | 1983-06-15 | $7700.00 | Window Closed / Lapsed |