US3584308A
Expired / Lapsed
US
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Bidirectional logic circuits employing dual standard arrays of bistable multivibrators
Assignee: United States Atomic Energy Commission
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Filing: 1969-06-11
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Granted: 1971-06-08
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Expires: 1989-06-11
Abstract
Abstract A bidirectional shift register or counter that is a composite of two standard serial arrays of bistable multivibrator elements wherein the outputs of each element of each array are directly connected to the outputs of the corresponding element in the other array; and the arrays are arranged to be actuated to move values in opposite directions. Only one array at a time is supplied with a shift or count pulse so that corresponding elements of each array, because of their interconnections, are always set to the same value. The values in both arrays, therefore, may be moved in either direction depending on which array is actuated with a shifting or counting pulse.
Inventors
- 👤 Franklin D Neu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:52
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
A bidirectional logic circuit comprising: a. a first array of bistable elements serially connected for movement of values in a first direction, each of Said elements in said first array having first and second unbuffered outputs; b. a second array of bistable elements serially connected for movement of values in a second direction, each of said elements in said second array having first and second unbuffered outputs, and each of said elements in said second array having complementary ordinal correspondence with an element in said first array; and c. means for connecting said first and second outputs of each element of said second array to said first and second outputs of the corresponding bistable element in said first array for setting the corresponding element of said first and second arrays to the same state, said means being comprised solely of a plurality of electrical conductors, each of said first outputs of said first array being connected directly to the first output of the corresponding element in said second array by one of said plurality of electrical conductors, and each of said second outputs of said first array being connected directly to the second output of the corresponding element in said second array by another of said plurality of electrical conductors.
Claim 2
Dependent Claim
210 words
A bidirectional logic circuit comprising: a. a first array of bistable elements serially connected for movement of values in a first direction, each of Said elements in said first array having first and second unbuffered outputs; b. a second array of bistable elements serially connected for movement of values in a second direction, each of said elements in said second array having first and second unbuffered outputs, and each of said elements in said second array having complementary ordinal correspondence with an element in said first array; and c. means for connecting said first and second outputs of each element of said second array to said first and second outputs of the corresponding bistable element in said first array for setting the corresponding element of said first and second arrays to the same state, said means being comprised solely of a plurality of electrical conductors, each of said first outputs of said first array being connected directly to the first output of the corresponding element in said second array by one of said plurality of electrical conductors, and each of said second outputs of said first array being connected directly to the second output of the corresponding element in said second array by another of said plurality of electrical conductors.
Claim 3
Dependent Claim
63 words
The bidirectional logic circuit of claim 1 wherein said first array of bistable elements is connected as a right shift register having zero and one data input terminals and zero and one data output terminals, and said second array of bistable elements is serially connected as a left-shift register having zero and one data input terminals and zero and one data output terminals.
Claim 4
Dependent Claim
71 words
The bidirectional logic circuit of claim 2 wherein said right shift register has its zero and one data output terminals connected to its one and zero data input terminals respectively for operation as a switch tail up-counter, and wherein said left-shift register has its zero and one data output terminals connected to its one and zero data input terminals respectively for operation as a down-counter for counting in said second direction.
Claim 5
Dependent Claim
30 words
The bidirectional logic circuit of claim 1 wherein said bistable elements of said first array and said bistable elements of said second array are standard JK flip-flops having unbuffered outputs.
Claim 6
Dependent Claim
61 words
The bidirectional logic circuit of claim 1 wherein a first shift line is connected to each of said elements of said first array for shifting values in said first array in said first direction, and a second shift line is connected to each of said elements of said second array for shifting values in said second array in said second direction.
Claim 7
Dependent Claim
54 words
The bidirectional logic circuit of claim 1 constituting a first bidirectional logic circuit, and further including a second one of said bidirectional logic circuits having the zero and one outputs of one of its elements connected respectively to the zero and one outputs of one of the elements of said first bidirectional logic circuit.
Claim 8
Dependent Claim
55 words
The bidirectional logic circuit of claim 1 further including a plurality of said bidirectional logic circuits, each of said plurality of bidirectional logic circuits having the zero and one outputs of one of its elements connected respectively to the zero and one outputs of one of the elements of each of the other bidirectional circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-07 | 1974-12-07 | 1975-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-07 | 1978-12-07 | 1979-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-07 | 1982-12-07 | 1983-06-08 | $7700.00 | Window Closed / Lapsed |