Squelch tail eliminator for dual squelch

Claim 2

A squelch circuit for a receiver including a first portion adapted to receive a tone and audio modulated carrier signal and to develop audio signals and a tone signal therefrom, said circuit including in combination, an audio portion coupled to the first receiver portion for reproducing the audio signals, said audio portion being adapted to be enabled in response to an enabling signal applied thereto, carrier squelch means coupled to the first portion and responsive to the carrier signal to develop a first control signal, tone coded squelch means coupled to the first portion and responsive to the tone signal to develop a second control signal, enabling signal means coupled to said audio portion and to said carrier squelch means and said tone coded squelch means, said enabling signal means providing an enabling signal in response to any one of said first and second control signals, and control means coupling said tone coded squelch means to said carrier squelch means and responsive to said second control signal to develop an inhibit signal and apply the same to said carrier squelch means, said carrier squelch means being responsive to said inhibit signal to be thereby rendered inoperative to devElop said first control signal.

Claim 3

The squelch circuit of claim 1 wherein said control means includes memory means for holding said carrier squelch means inoperative for a given time period.

Claim 4

The squelch circuit of claim 1 wherein, said control means acts in response to said second control signal to clamp the output signal from said carrier squelch means to a reference potential.

Claim 5

The squelch circuit of claim 1 wherein, said audio portion includes audio circuit means and gate means coupling the first receiver portion to said audio circuit means, said enabling signal means being coupled to said gate means for applying said enabling signal thereto, whereby said gate means acts to couple audio signals from the first receiver portion to said audio circuit means.

Claim 6

The squelch circuit of claim 4 wherein said control means includes a transistor having first and second electrodes and a control electrode, resistor means coupling said first electrode to said carrier squelch means, means coupling said second electrode to a reference potential, and means coupling said control electrode to said tone coded squelch means for receiving said second control signal, said transistor being responsive to said second control signal to be biased to provide conduction between said first and second electrodes to thereby couple said carrier squelch means to said reference potential through said resistor means.

Claim 7

The squelch circuit of claim 5 wherein, said first electrode is a collector electrode, said second electrode is an emitter electrode and said control electrode is a base electrode.

Claim 8

The squelch circuit of claim 1 including switch means for selectively connecting said carrier squelch means to the first portion of the receiver. 8, A squelch circuit with noise burst prevention for use with a dual squelch receiver which includes a first portion adapted to receive a tone and audio modulated carrier signal, an audio portion for reproducing the audio signals, carrier squelch means responsive to received carrier signals to develop a first control signal after a time delay, tone coded squelch means responsive to received tone signals to develop a second control signal, and means coupling the carrier squelch means and the tone coded squelch means to the audio portion for enabling the same in response to either of said first and second control signals, said squelch circuit including control means coupled to the tone coded squelch means and responsive to the second control signal to develop an inhibit signal, and means coupling said control means to the carrier squelch means to render the same inoperative in response to said inhibit signal, said control means including delay means for holding the carrier squelch means inoperative for a period longer than the time delay of the carrier squelch means so that reproduction of noise during such time delay is prevented.

Claim 9

The squelch circuit of claim 8 wherein said control means includes a transistor having first and second electrodes and a control electrode, resistor means coupling said first electrode to said carrier squelch means, means coupling said second electrode to a reference potential, and means coupling said control electrode to said tone coded squelch means for receiving said second control signal, said transistor being responsive to said second control signal to be biased to provide conduction between said first and second electrodes to thereby couple said carrier squelch means to said reference potential through said resistor means.

Claim 10

The squelch circuit of claim 8 including hook switch means for selectively rendering said carrier squelch means operative and inoperative, said hook switch means being operative in the release position thereof to render said carrier squelch means operative.